Can I use the the measured time between the first count and the last count in a fixed time window in order to increase the accuracy of a quadrature velocity measurement?

Question

I am measuring velocity using a linear encoder. Resolution is 40microns, sample frequency is 1MHz and the real velocity is oscillatory in nature with an amplitude of 200 to 400 mm/s with a freq of about 1Hz. We use a 5ms fixed time window to measure velocity. The quanization error for this is 8mm/s. Can I get rid of the quatization error by somehow measuring the exact time from the first pulse to the last pulse in the measurement window?

Answer 1

There is probably a way to do it, but it it may be easier to use an X-series board for the job.   They support a new counter capability for count reset on a digital edge without needing to be configured in encoder position mode.  I am not sure exactly how that feature's been implemented however, so maybe it won't make things easier after all.
The plan based on the hoped-for behavior: 
1. Configure an X-series counter for pulse generation based on "ticks" of your clock channel.
2. Set both initial delay and low time to the critical # of ticks.
3. Configure for count reset on a digital edge (if possible in pulse generation mode)
4. Configure the count reset value to be the critical # (or possibly 1 less, if possible in pulse generation mode)
5. If you want the output to remain high indefinitely, configure the counter task to use its own output as a
pause trigger, and pause while high.
The way pulse generation works is to preload a # of "low time" ticks into the count register.  Then every source edge will decrement the count.  When the count reaches terminal count (0), the counter's output is toggled (or can be configured to pulse).  The register is then loaded with the # of "high time" ticks and the process continues.
You would be perpetually interrupting the count-down process as long as you got your triggers in time.  The count would keep getting reset to the # of low counts, keep decrementing toward 0 without reaching it, and so on.  If ever you did reach 0, the output state would toggle high, then the high state would prevent subsequent clock signals from decrementing the count.
You can conceivably do a similar thing with a 6601, but I'm pretty sure you'd need 2 counters working together to get it working.
-Kevin P