Clock Multiplication of a clock of unkown frequency

I am building serializer and need to create a clock. I know that clock has to faster than the parallel clock that I have in my design. The problem I have is that I don't know what the frequency of the clock for the parallel data and the frequency may change. I have come up with a solution for discovering what the frequency of the parallel clock is, but I do not know how to generate a clock that is fast enough. I am only familiar with clock division. Is there a way that I could use the clock wizard IP? Any help would be greatly appreciated.
I am using Vivado 2015.1 and the board that I am using is the KC705.
~David Schumerth

You have to be very careful with this...
The MMCM is based on a VCO. The VCO frequency is determined by a formula - Fvco = Fin *M/D, where M and D are dividers that are (normally) set statically by the bitstream. As Fin changes, the resulting VCO frequency and hence output frequencies will scale with Fin. However, this can only be done within legal ranges of the VCO (and the Phase Frequncy Detector - PFD). Both of these have defined maximum and minimum values - you cannot go outside either range.
The range of Fvco (depending on speed grade) is around 2:1 (or 2.5:1 in faster speedgrades). So if your input frequency changes by more than this ratio, the VCO will not be able to lock at all frequencies with the same M and D values.
If you need to lock at wider frequency ranges or if you need to create constant output frequencies regardless of Fin, then you will need to dynamically program the MMCM; change the M and D values (and O values) depening on your Fin. To do so, you will have to have some mechanism of measuring the input frequency (which will need at least one constant frequency clock that does not come from or through the MMCM), and then use the Dynamic Reconfiguration Port (DRP) of the MMCM to change the divider values. This is not trivially easy to do, as the DRP provides access to blocks of MMCM registers that must all be set consistently for the mode change. Furthermore, the MMCM must be reset after DRP changes (so the clock will stop and have to wait for the MMCM to relock).
This will all require a fairly complicated state machine or a small microcontroller to manage... This is all well outside the scope of what the clocking wizard will do for you - you will have to design all this stuff yourself and manually instantiate the MMCM (along with the controller for managing the DRP).
Avrum

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Solved!
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Multiple PRI ports clocking issue

Hello,
We have a 3845 with 2 VWIC2-2MFT-G703 cards. The router is between Telcos and another 3945.
This router acts as a forwarder, fax gateway, etc. We are working with 2 Telcos and we are getting voice service.
3845 has 4 PRI ports. 2 of them are connected to Telcos and they are on the first VWIC2 card and the other 2 is connected to 3945 which is the main device for our IP Telephony.
Telco1---- -----
3845 3945
Telco2---- -----
I have the following commands for network clock:
network-clock-participate wic 0
network-clock-participate wic 1
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network-clock-select 2 E1 0/0/1
Telco1 has no slip errors since it is the master clock source.
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We can not use clock source line independent since this is a voice line.
3845 acts as network side for the connections between 3845 and 3945. We do have slip errors on these connections as well.
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Here is E1 controllers status:
E1 0/0/0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
Data in current interval (238 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
0 Line Code Violations, 0 Path Code Violations,
0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/0/1 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is CRC4, Line Code is HDB3, Clock Source is Line.
Data in current interval (239 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
30 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
30 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
0 Line Code Violations, 0 Path Code Violations,
10938 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
10938 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/1/0 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
Data in current interval (238 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
84 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
84 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
0 Line Code Violations, 0 Path Code Violations,
30432 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
30432 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
E1 0/1/1 is up.
Applique type is Channelized E1 - balanced
No alarms detected.
alarm-trigger is not set
Version info Firmware: 20100222, FPGA: 13, spm_count = 0
Framing is NO-CRC4, Line Code is HDB3, Clock Source is Line.
Data in current interval (239 seconds elapsed):
0 Line Code Violations, 0 Path Code Violations
53 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
53 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
Total Data (last 24 hours)
0 Line Code Violations, 0 Path Code Violations,
4259 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins,
4259 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs

If the appropriate IOS images are used with all the supported hardware, then there should not be any issues. Guess, you have enough memory too for the required images.

Multiple clock domains each with clock mulitplexing. Solve warning (Place 30-568])

My design can be partitioned in several clock regions (up to 20 for now). In each region I've instantiated a PLL and each PLL generates 4 clocks. I need to multiplex these 4 clocks per each region and to clock gate the output based on a signal in the fabric logic.
I know the a proper way of doing it would be to use 3 BUFGMUX components followed by a BUFGCE, however this has issues:
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I tried to multiplex the the first level of clocks with the fabric logic (simple MUXes in RTL) and then to multiplex them with a BUFGCTRL.
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clk0 _
|_
_ RTL_MUX (LUT)___
clk1 _| |
|__
clk2 _ __BUFGCTRL____BUFGCE_______logic
|_ | |
_ RTL_MUX (LUT)____| |__clock_gating/selection_logic
clk3 _|
This attempt worked with a portion of the design and everything runs correctly. However when I instantiate the entire design (rougtly 50% occupation on the V2000), Vivado is unable to fix hold violations.
In addition, with both the full design and the smaller portion, I still warnings, which I don't know how to resolve. Maybe if I could fix those, I would have more chances to get a working design.
This is the warning I'm getting:
[Place 30-568] A LUT 'clkmux_3/bufgctrl_1_i_2' is driving clock pin of 24 registers. This could lead to large hold time violations. First few involved registers are:
I checked the schematic and the clocks multiplexed with the LUTs go straight to the BUFGCTRL, which is the one driving the registers listed in the warming. Does this mean that even if I use a BUFG, Vivado is still detecting that the clock originates from an LUT (the input to the BUFG)? Do you know a workaround?
Thank you in advance. Kind regards.
Paolo

Hi,
Ideally what you are trying to do is using gated clocks. Clock should in general not be gated through LUT's or fabric logic. You should use buffers to do that. However in your case, considering you have taken care of the hold violations and the timing, you can safely ignore these warnings. This warnings just warns you about the clock gating throught he LUT's which might affect the device timing. Write proper timing constraints and make sure you meet timing. That shoud do.

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How do i draw a clock showing 3'0 Clock??

Hi
This is the code for a clock im drawing. However, i need it to show 3'0 clock, with the second hand at 7, but now all the needle is pointing at 12. How and what do i change? Hope someone can explain to me clearly what to do cos' im quite blur.
import java.awt.*;
import javax.swing.*;
class DisplayClock extends JFrame
public static void main(String[] args)
int hour = 0;
int minute = 0;
int second = 0;
if (args.length > 3) {
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System.exit(0);
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minute = new Integer(args[1]).intValue();
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frame.setDefaultCloseOperation(JFrame.EXIT_ON_CLOSE);
frame.setSize(300, 200);
frame.setVisible(true);
class DrawClock extends JPanel
private int hour;
private int minute;
private int second;
protected int xCenter, yCenter;
protected int clockRadius;
public DrawClock(int hour, int minute, int second)
this.hour = hour;
this.minute = minute;
this.second = second;
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super.paintComponent(g);
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xCenter = (getSize().width)/2;
yCenter = (getSize().height)/2;
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g.drawString("3", xCenter+clockRadius+75, yCenter+3);
g.drawString("6", xCenter-3, yCenter+clockRadius+10);
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int sLength = (int)(clockRadius*0.9);
int xSecond = (int)(xCenter + sLength*Math.sin(second*(2*Math.PI/60)));
int ySecond = (int)(yCenter - sLength*Math.cos(second*(2*Math.PI/60)));
g.setColor(Color.red);
g.drawLine(xCenter, yCenter, xSecond, ySecond);
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int mLength = (int)(clockRadius*0.75);
int xMinute = (int)(xCenter + mLength*Math.sin(minute*(2*Math.PI/60)));
int yMinute = (int)(yCenter - mLength*Math.cos(minute*(2*Math.PI/60)));
g.setColor(Color.black);
g.drawLine(xCenter, yCenter, xMinute, yMinute);
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int hLength = (int)(clockRadius*0.75);
int xHour = (int)(xCenter +
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Before people complain...
import java.awt.*;
import javax.swing.*;
class DisplayClock extends JFrame
public static void main(String[] args)
int hour = 0;
int minute = 0;
int second = 0;
if (args.length > 3) {
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private int hour;
private int minute;
private int second;
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g.drawLine(xCenter, yCenter, xMinute, yMinute);
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int xHour = (int)(xCenter +
hLength*Math.sin((hour+minute/60.0)*(2*Math.PI/12)));
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Regarding Clocking wizard and Simulation clock generation - document and their uses VIVADO IPI

While working with Vivado IPI , I came across two different IPs, one is simulation clock and the other is clocking wizard IP.
But got error while generating wrapper of these IPs with the steps I did , I am unable to instantiate the IP of simulation clock generation version 1 of 2014.4.1 vivado. And get error "Clk gen" not found.
So, can you please just give me correct direction whether these can be used together, that is input of clocking wizard IP is simulation clock generation IP ( please correct if i am wrong) or I need to make external port in clocking wizard and assign Y9 pin of zedboard to that.
In brief, I want to know the uses of these IPs w.r.t to some sequential design , please just elaborate theoretical example even.

What do you want to do? Simulation only CLOCK Generator is only for simulation purpose.
Can you please just give me correct direction whether these can be used together, that is input of clocking wizard IP is simulation clock generation IP
--> No
I need to make external port in clocking wizard and assign Y9 pin of zedboard to that
--> Yes, Use the cloking Wizard

Converting 24 hour clock to 12 hour clock using JS

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Does this help?
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Good Evening,
This morning I turned on my MacBook Pro and while I was typing my password to log in, I noticed that the time in the login window clock had a wrong setting. The time displayed was 4 hours delayed in relation to my time zone. However, after logging into my user account I looked and the menu bar and when the clock got displayed, the correct time of my time zone appeared.
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Make sure the time and date are correct.
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Lock screen clock changed to analog clock

I use either Sony clock or digital clock on lock screen. However, it will get changed to analog clock for no reason. Few times already. Changed it back to digital/Sony clock, but it goes back to analog clock after awhile (days).
Anyone see this behavior? Any way to make the Sony/digital clock to stick?
Thanks.
Solved!
Go to Solution.

I have not experienced this behaviour and just like Thommo said, the clock should stick as long as you don't change it or have any application that affect it. Are you sure that you lock the screen when you put the phone in your pocket or similar?
- Official Sony Xperia Support Staff
If you're new to our forums make sure that you have read our Discussion guidelines.
If you want to get in touch with the local support team for your country please visit our contact page.

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Thanks. That's good news.
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Vivado 2014.2 MMCM and BUFGMUX multiple syncronous clock

Hi,
I am working on KC705 and I use Vivado 2014.2. The block diagram of the clocking structure and the system as below.
I generated 3 clocks (250 MHz, 125 MHz, 62.5 MHz) from the input clock (250 MHz). Because of the BUFG-BUFG error I select clocking wizard output with no buffer option. Then I select the clocks by using BUFGMUX. Finally, I have 4 clocks that I used in the whole design. All clocks should be synchronous to each other.
How can I constraint these clocks? I tried to specify period seperately for each clock but the timing did not met.
Thanks,
Muhammet

So, first, you don't need to add any constraints. You don't say how the clocks are generated, but I assume you are using an MMCM. If so, then the tool can derive all the clocks from the input clocks - simply do a create_clock on the input clock and all the other clocks will be automatically generated (you don't need any create_generated_clock commands).
The multiplexed clock will be complicated - the output of the two cascaded BUFGMUXes will carry all three clocks; the 250, the 125 and the 62.5. The tools will actually perform timing analysis on all FFs on this domain 8 times - between each pair of clocks. But, since all the clocks are multiples of eachother, this will effectively constrain paths to the 250MHz clock.
The paths between the multiplexed clock and all other clock domains will be effectively timed at 250MHz. Assuming that there are legal crossings between the MUXed clock and all three domains (regardless of which mode is selected for the MUXed clock), this too is correct. If there are some restrictions (like there will never be an active path from the MUXed domain to the 62.5MHz domain when the MUXed domain is selecting one of the faster clocks), then exceptions will be required to loosen the requirements on these paths.
All that being said, this is a BAD thing to do in an FPGA. Having different outputs of an MMCM take paths through different numbers of BUFGs introduces very nasty clock skew between the different domains. This will result in huge hold time violations that need to be fixed between the un-MUXed domains and the MUXed domain. This will likely fail timing analysis, and even if it does pass, will require lots of extra routing resources to fix the hold violations.
I am not entirely certain what you are trying to accomplish by using the different domains. Since the 250MHz clock can be selected, all logic will have to be able to run at that speed, so there is no timing advantage to using the slower domains. If the slower domains are needed for functional reasons, then, rather than using clock MUXing, I would suggest using a single BUFGCE for the "multiplexed" domain, driven by the 250MHz output of the MMCM, and enabling the CE all the time (for 250MHz operation), every other clock (for 125MHz operation), or every 4th clock (for 62.5MHz operation). Using the BUFGCE, no generated clocks will be created - the tool will view the BUFGCE as a simple clock buffer, and everything will end up being timed on the 250MHz domain. In this case, there is only one domain on the output of the BUFGCE (250MHz), rather than 3 clocks - this will actually speed up place and route (since there are less timing paths).
All 4 domains will end up going through exactly one BUFG or BUFGCE (which are identical resources), and hence will have no extra clock skew - this will avoid the hold time issue I described above.
The only caveat is if you are planning to use the falling edge of the "multiplexed" domain. In all modes, the clock will be high for only one half period of the 250MHz domain; for 250MHz operation this will result in a normal 50/50 duty cycle. For 125MHz, though, the duty cycle will only be 25% and for the 62.5 it will be 12.5%. Again, this is only an issue if you use the falling edge for clocking logic (which is a bad design practice) or if you use an IDDR or ODDR for interfaces.
Avrum

Frequency generator to clock counters

I recently purchased a PCI-6221 with 2 32-bit counters. I wish to read and log two encoders (hence the 6221) and several analog inputs simultaneously.. My research found that this is not possible without an external clock (which can be created using one of the counters) leaving only one counter for my encoders. I noticed the 6221 has one Frequency Generator. Can this generator be used as a clock source for the counters and the AI?
Jeff
Solved!
Go to Solution.

You can use Freq Out as the sample clock of both CI tasks. However, you are restricted to what frequencies you can generated. You should also be able to use the AI sample clock as the "sample clock source" of the CI tasks.
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http://www.ni.com/support

Clock domain crossing FIFO sanity check

Hi all,
I am having an issue with producing a one clock cycle wide pulse output. I have dealt with crossing clock domains before but I just want to make sure I am not doing anything wrong.
I have two clock domains that are mesochronous, both are 250MHz from two different external devices that are deskewed in a DCM.
I generate a 1 clock cycle wide pulse from clock domain 1 periodically. I need this pulse to cross the domain coherently into clock domain 2 so that the period remains the same. In other words the latency from crossing clock domains must have a a constant latency (the amount of latency does not matter as long as it is the same all the time).
I am using a coregen generated asynchronous block RAM FIFO. The write enable is the pulse output from clock domain 1 and the empty flag of the FIFO is the output pulse (except I negate it and register the output in an IOB FF clocked with clock domain 2s clock). The output FF is actually a FDCPE, since it is necessary on power up to send an asynchronous '1' to the device. Once the asynchronous '1' is outputted, it is cleared and never used again. I am guessing that an FDCPE primitive will act the same as a FF.
Here is the issue:
On power up, if it works, it will continue to work at all temperatures for as along as the system is powered on. If on power up it does not work, it will continue to not work for as long as the system is powered on. I am assuming this is a power-on phase issue. Would this have something to do with how I am crossing the clock domains or should I look elsewhere?
When I say it does not work I mean:
Clock domain 1 is from an ADC and clock domain 2 is from a device similar to a DAC. The output of the DAC feeds back into the ADC. When it does work, the output I create from the DAC is coherently read from the ADC. When it does not work, it looks as if the DAC output is started at different clock cycles (multiple phase shifts). This is why I am assuming that it is due to signal coherency, but we have used this scheme for crossing clock domains multiple times and it has always worked without any issues.
Sorry if this is not enough information.
Thanks

I don't entirely understand the description of the problem you are seeing - we need more context for that. But I will address the clock crossing.
I don't see anything fundamentally wrong with the clock crossing mechanism you are describing. However, it is VERY expensive for what you are using it for. In fact, even though you are using a clock crossing FIFO, you aren't actually using the storage of the FIFO - you are just using the address counters and full/empty flag generation (which is implemented in fabric logic), and completely ignoring/wasting the RAM.
There are many simple circuits for doing this clock crossing. As long as you can ensure that you will never get one pulse less than 3 (maybe even 2) after the previous one, then the circuit shown below (a toggle event synchronizer) is simple cheap and effective
This circuit takes your pulse event on the source clock domain, converts it into a toggle event, which is then synchronized through a two stage synchronizer and then edge detected in the destination domain.
You don't say what tool you are using (Vivado or ISE) - in either tool it will need some constraints.
In Vivado, you should set the ASYNC_REG property on the two middle flip-flops
set_property ASYNC_REG TRUE [get_cells {signal_meta_reg signal_dst_reg}]
You will also need some sort of exception on the clock crossing (since all clocks in Vivado are related by default). My preferred one is
set_max_delay -datapath_only 4 -from [get_cells event_toggle_reg] -to [get_cells signal_meta_reg]
You should still use this even though both clocks are 4ns periods (so the requirement will end up being 4ns anyway) but the -datapath_only flag tells the tools not to analyze the clock insertion... Furthermore, on this synchronizer, a max_delay isn't technically needed (since there is only one signal being synchronized), so you could set the path as being false, but it is good habit to use this constraint anyway, since other synchronizers need it.
If you can't guarantee that there are 2 clocks between events, then you can use a simple Gray code counter on the source domain to count events, and send the count to the destination side, which will generate one output pulse for each count received - this is basically what the logic in the FIFO is doing, but without carrying around the useless RAM.
And, by the way, if you are going to stick to the FIFO, why not use a distributed RAM based FIFO - you won't need to waste the block RAM... If you make it 64x1, then you will only waste two LUTs for the useless RAM instead of an entire block RAM.
Not that this matters, but you say that the clocks are mesochronous - are they really? To be mesochronous, they need to derive from the same oscillator; they may go through very different paths, but they must come from the same frequency source. Merely both being 250MHz does not make them mesochronous (but, as I say, that doesn't matter for this clock crosser ).
As for the rest of it - I don't think the clock crossing is the source of your problem. Its vaguely possible that you are messing up the FIFO logic by giving it a pulse too close to the deassertion of the reset; the built-in FIFOs have a requirement that the WR_EN not be asserted within a handful of clocks after the deassertion of rst. But you say you are using the block RAM based one, which probably doesn't need this. So its probably not the clock crosser...
Avrum

Clock Multiplication of a clock of unkown frequency

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