Data Transfer methods between FPGA and RT

Question

I have 10 values that I combined into a cluster that I want to send to the RT controller.  The problem is if I just the read/write FPGA, I only get 1/10th of the data.  I am assuming that it is the time taking to transfer from FPGA to RT.  So I looked into DMA FIFO.  When I use this, I do capture the data, but I notice jumps/shifts in the data.  It's almost like the buffer fills up, and then dumps it at the last sec. To reduce this, I went from 10 values from the cluster to 2, and there were not shifts/jumps.  The problem is I need all 10 values.  So I'm wondering if I need to increase my DMA FIFO or if there is another meathod I need to use like Shared Varibles? 
Thanks,
guilio

Answer 1

The one thing I still don't understand is what you mean by this "jump" in your data. Can you be a bit more specific about this? What I mean by jump.  The elements coming from the FIFO in the RT controller will display on my array visual aid normally.  Then you will see the data jump. Here is an example.  I am bringing out 3 elements, X Y Z into an array.  I'll read lets say 9 elements at a time.  So my array, after I transform it into a 2D array for saving will look like this.  [x y z;x y z;x y z].  At some points in time, the array will jump and look like this. [x y z;z x y ;z x y].  Then it will go back to how I expect it to look [z x y;x y z;x y z].  Right now, I am reading ~3000 elements.  The elements remaining depends on what else is going on.  If the visual aids are deleted, then elements remaining will never max out and thus, I won't get jumps.  If I put visual aids in, then I get jumps because elements remaining maxes out.  This leads me to believe that the FIFO is filling up and since it can't release all the information fast enough, then it just dumps it and fill it up again.  The weird thing about it, It doesn't happen in a pattern (every 3000 elements).  I tried putting them in seperate loops, it still slows things down.  I tried queing/dequeing, still slows it down.  I need to be able to read all elements fo all 3 DMA transfers at once.   Maybe it will help us locate the problem.  Otherwise, your DMA FIFO looks OK.  Can you verify the number of times your data is written to the FIFO from the FPGA? When I put a clock in to measure loops speed, it was showing 8-9us.  I can't have this no more than 10us or I will missed data. I would like to see a definite count of this.  Then on the RT side, what does the "Elements Remaining" output look like?  As before, elements remaining depends on what else is going on.  If I just have the DMA FIFO's, then I can adjust the read elements number so all three don't max out, but as soon as I put something else in, it will max out.  Since this is a FIFO we should be able to keep very close track of elements in and out.
Let me know if you need more info.  I know about the FXP point transfer, unfotunately, not all my FXP elements are the same data type.
Thanks,
guilio