Does not compile on LV 2013, but works fine on LV 2012 SP1

Question

I have an FPGA VI that compiles without issue with LV 2012 SP1, but does not work with LV 2013 and Xilinx Tools version 14.4. Why is this happening? I have attached the compiler log file.
Attachments:
XilinxLog.txt ‏1468 KB

Answer 1

ba_0101,
2012 SP1 and 2013 both use different versions of the xilinx compilation tools. As we don't produce that software it's hard to say exactly what may have changed in their implementation that is causing the compilation to fail. A quick look at the logs uncovers this error during the placement phase:
ERROR:Place:120 - There were not enough sites to place all selected components.
Some of these failures can be circumvented by using an alternate algorithm
(though it may take longer run time). If you would like to enable this
algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1
and try again
It looks to me like this error stems from this:
ERROR:Place:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Which is a simple resource overmapping error. It looks like your design is rather large based on the rest of the logs. Am I correct in assuming this? During the compilation, what do the pre-synthesis device utilization reports estimate?
With large designs it is common to sometimes have successful compilations and sometimes not due to the random nature of the compiler during the place and route phases. Does the design consistently fail in 2013 accross several compilation attempts?
If you continue to see consistent failures, Xilinx's support documentation for this error suggests using setting an environment variable within the compile tools to use a different algorithm in the P&R phase. According to the documentation, this algorithm may take longer to execute, however it should improve the likelihood that your design successfully compiles. 
Additionally, if the design is just over utilization, you may benefit most by searching your design for areas that could be quickly and easily optimized to decrease resource utilization. I hope this information helps, please post back if you have any further questions.
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments