FPGA DMA Size Allocation

Hi all,
My application involves grabbing images from a 3-taps, 16-bit camera using FlexRIO. The PXI controller I am using is Windows-based while the FlexRIO module that I have is a PXI-7954 + NI 1483 adapter. The size of the image I am grabbing is 2560 x 2160, U16 and the clock cycle is 100 MHz. I've been trying for over a week and up to today, I still am not able to get the image from the camera as I kept on getting the DMA Write Timeout error. Right now, the DMA size in the FPGA is set at 130k but whenever I tried to increase this further, I get a compilation error. I've tried to have the host program to grab 100k data points from the FPGA DMA at every milisecond but it seems that, I am capped at about 10-15ms. Perhaps, Windows has its own limitation...
Attached is the program that I am using, modified from the LabVIEW shipped example. Please advice, how do move forward from here? or, is it possible to further increase the DMA buffer size up 10x higher than the current limit?
Attachments:
1-Tap 10-Bit Camera with Frame Trigger.zip ‏1684 KB

Hi Shazlan
Apologies for taking so long to reply to you.
You are correct in saying that the latest driver is IMAQ 4.6.4 and this can be downloaded from our website if you have not done so already.
If you have already installed the IMAX 4.6.4 driver, has this managed to resolve your issue?
Also, have you tried to run the compilation again and obtained a report outlining the problems?
As a side note - I have been looking into the possibility of downloading some sort of driver for the Samos camera you are using from Andorra. While National Instruments have not created a driver for this device, Andorra do have a Software Development Kit (SDK) which they say works with LabVIEW. You may find it useful to have this so that you no longer have to write the driver yourself. This may then save resources on the FPGA.
Keep me updated on your progress and I will continue to look into this issue for you.
Regards
Marshall B
Applications Engineer
National Instruments UK & Ireland

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5640R FPGA Examples: Samples missing at multiples of DMA-Size

Hi all,
We have started working in NI-5640R IF-RIO with Labview-2011.
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Hi Chris,
>>Did you use the Asynch Analog Input Example as it is out of the box or did you make any modifications?
   Yes i used it "as-it-is". Just added a Measurement-FIle at the I/Q output to visualize the results offline.
>>When you are talking about changing the DMA FIFO size, are you referring to the host side or the FPGA?
     I am reffering to "DMA-Read Number-of-Elements" see image below. In examples this parameter is same as "AI-Samples-to-Acquire"
>>From looking at the example, it looks like the host buffer is set to 1M elements, and the FPGA side to 16,383
    Yes this is correct and i didnot changed this settings
>> Is there a chance you are changing the samples to acquire (That starts at a default of 5,000)?
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Hi there,
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Hi Weny,
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Hi,
We're having trouble using the Host to FPGA DMA feature available in
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An internal software error has occurred.
Please contact National Instruments technical support at ni.com/support
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----abhay

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Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
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ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
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Bogdan
Solved!
Go to Solution.
Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
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I have a pair of Flex RIO 7966r boards where I am trying to perform DRAM to DMA transfers. Each FPGA uses both banks of DRAM. One bank for capturing Camera Link frames, the other bank for capturing sub-frames from within each frame (And performing some processing on the sub-frame data).
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Hey xl600,
I'm not immediately sure how to have ISim display the DMA Engine behavior, but I'll see if I can I dig anything up for you. I've come across a couple of other users encountering issues with FIFO signals appearing in ISim over on the Xilinx forums, so it might be worthwhile to post there as well in case it happens to be due to ISim itself.
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LabVIEW stores booleans as a U8 in memory according to the article.
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Unofficial Forum Rules and Guidelines - Hooovahh - LabVIEW Overlord
If 10 out of 10 experts in any field say something is bad, you should probably take their opinion seriously.
Solved!
Go to Solution.

Hooovahh wrote:
LabVIEW stores booleans as a U8 in memory according to the article.
http://zone.ni.com/reference/en-XX/help/371361J-01/lvconcepts/how_labview_stores_data_in_memory/
My question is what happens when you develop in FPGA? Specifically if I made 8 lookup tables with the data type being a boolean, does that take the same amount of resources as a single U8 lookup table? Or is it taking as much resources as 8 U8 lookup tables?
I am not 100% sure, but I believe on FPGA a boolean is actually treated as a bit, not a byte. The u8 representation is due to a byte being the smallest addressable unit in a PC type environment. (At least I think this is correct. Someone smarter than me may say otherwise).
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Rt fpga dma timeout not waiting

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jonnnnnnn wrote:
Hello
I have a Target to Host DMA between. The read function sits in a while loop with a 2000ms timeout. Upon timeout it loops round and recalls the read function. On the second, and subsequent calls, it does not wait for the timeout time. I assume that this is because it was already itemed out. The error is wired to a shift register.
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Is there a way to clear the timeout?
If i change it to an indefinite wait, is there a way to force the read to wake up?
Thanks
Does the timeout result in an error on the error line? Yes, errro -54000 if memory serves correctly. Did you try highlighting execution to see this...
Is there a way to clear the timeout? Don't wire -1, I got burned by this. The DMA actually polls in the background (I think but I never verified) so a negative timeout can slam your processor. You can maybe try interrupts, although I didn't use this method I just threw a not-too-long timeout on there and cleared the error if it was -54000
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CLA, LabVIEW Versions 2010-2013

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I have a question regarding the sending of data via FIFO to an FPGA card via DMA. I would assume that if I have several locations in my RT code sending data via DMA FIFO that it is still guaranteed that any given DMA Transfer (let's say 12 data values) are delivered atomically. That is to say that each DMA node data is sent as a contiguous block.
Take the following example. I have two DMA FIFO nodes in parallel. I don't know which is going to be executed first, and they will most of the time be vying for bandwidth. Both nodes send over the SAME DMA FIFO. Does the data arrive interleaved, or is each sent block guaranteed to be contiguous ont he receiving end. Do I end up with
Data0 (Faster node)
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I'm kind of assuming that they remain in a contiguous block which I'm also hoping for because I want to abuse the DMA FIFO as a built-in timing source for a specific functionality I require on my FPGA board. I can then use the RT-FPGA DMA Buffer to queue up my commands and still have them execute in perfect determinism (Until the end of the data in my single DMA transfer of course).
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Woah, new avatar. Confusing!
I am going to preface this by saying that I am making assumptions, and in no way is this a definitive answer. In general, I have always had to do FPGA to RT streaming through a FIFO and not the other way around.
When writing to the FPGA from the RT, does the FIFO.write method accept an array of data as the input? I'm assuming it does. If so, I'd then make the assumption that the node is blocking (like most everything else in LabVIEW). in which case the data would all be queued up contiguously. Interleaving would imply that two parallel writes would have to know about each other, and the program would wait for both writes to execute so that it could interleave the data. That doesn't seem possible (or if it was, this would be an awful design decision because what if one of the writes never executed).
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You're probably safe assuming the blocks are contigous. Can you test this by simulating the FPGA? If your'e really worried about interleaving, could you just wrap the FIFO.write method up in a subVI, that way you are 100% sure of the blocking?
Edit: Had a thought after I posted, how can you guarantee the order things are written to the FIFO? For example, what if the "slow" write actually executes first? Then your commands, while contiguous, will be "slower node" 1-12 then "faster node" 1-12. It seems to me you would have to serialize the two to ensure anything.
Sorry if I'm not fully understanding your question.
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Problem with the analog input acquisition in labview fpga 8.5.1 and CRIO

Hello all,
I am using NI CRIO 9104 RT controller with 9014 FPGA chassis.I am using an Analog input module 9205.My problem is with the acquisition.I am using a
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Difficult to see where is the problem ....
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