[FPGA] Loop rate very slow: Do FPGA I/O nodes in parallel loops block each other?

Hi,
I am using cRIO-9075. Mod1 is NI 9263, Mod2 is NI 9227, Mod3 is 9215.
Please see my VI attached or the given screenshot.
The FPGA code is based on the "NI CompactRIO Waveform Reference Library" (it's the lower loop).
The upper loop was added by me and is writing a waveform from blockmemory to the NI 9263 module (Mod 1).
The data sampled in the lower loop is running at 1 kHz. The control "AO Update Period" for the upper loop has a value of (for example) 10 (=uS).
The problem is, that this loop is running much much slower than it should. Once I disable the FPGA I/O node in the lower loop (as done in the attachments), it's running as fast as it should.
It seems to me, that the FPGA I/O nodes are blocking each other. I tried to figure it out by reading through serveral NI documents, but until now I have no idea how to solve that.
Can you give me some advices? Some general tipps about the VI?
Thanks!
Attachments:
FPGA Loop Rate.PNG ‏72 KB
FPGA Main.vi ‏251 KB

Hi, thanks so far.
Originally the control was inside the loop. Then I tried if it makes a difference if it's outside.
Ok, i really seems to be that default value of "100000" for "AO Update Period".
Starting the VI directly woks like expected. Having "AO Update period" inside the loop makes it possible to control it as it's running.
But, please see the attachment. When starting the FPGA through RT and setting the appropiate value, it does not seem to work. The oscilloscope show's the same behavior like "AO Update Period" was 100000.
But when reading the value of "AO Update Period" afterwards (while the FPGA is running), it shows the expected value of "10".
Having changed the default value to 10 works so far, but I am not able to changed it (see attachment).
So the problem is: Why is "Read/Write control" not working here? Why is still the default value used?
Attachments:
FPGA Loop Rate 2.PNG ‏5 KB

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Go to Solution.
Attachments:
Velocity Profile.png ‏21 KB

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[FPGA] Loop rate very slow: Do FPGA I/O nodes in parallel loops block each other?

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