Fpga:timin​g violation

Hola,
Dispongo de un cRIO 9074, con una FPGA spartan-3 2M. He diseñado una VI para generar una chirp desde la FPGA. La primera compilación no me generó error alguno, sin embargo, después he añadido la función de interrupción (adjunto VI), y por lo tanto un "sequence", y me ha dado error temporal (adjunto imagen con el error). Es extraño, porque la ocupación de la FPGA es baja (adjunto imagen con el resumen). No comprendo las ventanas donde se informa de los errores.
1.- Qué significa Non-diagram component? A qué ahace referencia?
2.- En base a qué se calculan los valores que aparecen en Cloks Maximun (Mhz)?
Se que para mejorar los tiempos hay que hacer pipeline, pero me gustaría comprender el origen de estos errores. He buscado información pero no doy con ella,
Gracias,
Attachments:
error con irq.jpg ‏149 KB
ocupacion.jpg ‏53 KB
chirp_FPGA.vi ‏48 KB

Hola aino!
Antes de nada, para conseguir que tu VI compile, te paso un link:
http://digital.ni.com/public.nsf/allkb/EE940C191DD​CE9CE86256E5500783A4D?OpenDocument
Después, lo primero que resalta de tu VI son los puntos de coerción (puntos rojos pequeños a la entrada). Para evitarlos, podrías poner todos los controles con la misma representación.
Para entender mejor lo que preguntas, hay un artículo en la ayuda de LV que te puede ayudar mejor que yo. El artículo se llama Timing Violation Analysis Window (de hecho hay un link a otro artículo que se llama Fixing Timing Violations que te puede ser de ayuda).
Ese parámetro del Clock Maximum se calcula con el la frecuencia de reloj mínima que necesita un determinado componente y la frecuencia máxima que tu placa le puede dar.
Espero haberte sido de aydua, un saludo!!
Applications Engineer - Certified LabVIEW Developer & Certified TestStand Developer

Similar Messages

  • "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

    The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA:  The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
    In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
    I tried to optimize my labview fpga vi with pipelining, but had no success.
    Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
    Software:
    Labview 2011, fpga 2011, xilinx tools 12.4 sp1
    Hardware:
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    NI PXIe-8108 Embedded controller
    NI PXIe-7965R FPGA FlexRIO FPGA module
    NI 5761 250 MS/s 14 bit Analog input digitizer
    The Xilinx log of the compilation run is attached.
    Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
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    Attachments:
    xilinxlogc.txt ‏2313 KB

    Hi Kyle,
    the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
    - You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
    - More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
    - More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
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  • FPGA Compile Error: Timing Violation

    All,
    I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.
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    Status: Compilation failed due to timing violations.
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    Device Utilization
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    Flip Flops: 28.5% (11692 out of 40960)
    Total LUTs: 45.9% (18788 out of 40960)
    Block RAMs: 0.0% (0 out of 40)
    Timing
    MiteClk (Used by non-diagram components): 33.04 MHz (69.24 MHz maximum)
    40 MHz Onboard Clock: 40.41 MHz (30.29 MHz maximum)
    Actual Xilinx Options
    Synthesis Optimization Goal: Speed
    Synthesis Optimization Effort: High
    Map Overall Effort Level: High
    Place and Route Overall Effort Level: High
    Start Time: 6/6/2010 10:11:47 PM
    End Time: 6/6/2010 10:57:33 PM 
    And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:
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    An internal error occurred. Please try again or contact National Instruments.
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    Error Text --> <APPEND>
    Additional Information: There is no matching tag in Xilinx twx file
    There is no matching tag in Xilinx twx file
    Also,
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    I've attached the code and the xflow.log! Thanks for your time!
    Thanks!
    Ken 
    Attachments:
    FPGA.zip ‏778 KB
    xflow.txt ‏1138 KB

    Hey Ken!
    If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.
    If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.
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    Caleb Harris
    National Instruments | Mechanical Engineer | http://www.ni.com/support

  • Compilation failed due to timing violations, Getting Xflow error and resources over use.

    Hi,
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    I would like to know is there any limitations in using fixed point functions?
    I am configuring all funtions as a 64 bit word length and 32 bit integer length in cofig parameter set up and all are outside the timed loop.
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    Status: Compilation failed due to timing violations.
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          - Reduce long arithmetic/combinatorial paths
          - Use pipelining within Timed Loops
          - Reduce the number of nested case structures
      * Reduce clock rates if possible
      * Recompile
    Refer to the LabVIEW Help for more information about resolving compilation errors. Click the Help button to display the LabVIEW Help.
    Compilation Summary
    Device Utilization Summary:
       Number of BUFGMUXs                        2 out of 16     12%
       Number of External IOBs                 214 out of 484    44%
          Number of LOCed IOBs                 214 out of 214   100%
       Number of MULT18X18s                     69 out of 96     71%
       Number of SLICEs                       4387 out of 14336  30%
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      Base clock: 40 MHz Onboard Clock
          Requested Rate:      40.408938MHz
          Achieved Rate:       36.974044MHz    <<<=== Timing Violation

    lion-o wrote:
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    Really? "Demo" is perhaps too strong a word, but the NI Labs page says that the toolkits there "aren't quite ready for release" and are "experimental prototype"s. My understanding was that they work, but are only meant to show potential future products and get feedback on them. If this is not the case, perhaps the wording needs to be changed.
    I know I wouldn't want to be using something throughout my code and then find out that it is not supported when the next LV version came out because it was only a prototype. Can you promise support into the future for these? If you can't, that should be clearly stated.
    Try to take over the world!

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    hey thu^^,
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  • How do i know if my fpga vi timing before i compile

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    Hi,
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    I hope that this helps!
    Thanks,
    Frank
    Application Engineer
    National Instruments

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