NI 9512 with Labview FPGA Interface

Is it possible to use the NI 9512 stepper drive module with the Labview FPGA interface or is it only possible to use it with the scan interface? When I try to add the module to an FPGA target, I get an error telling me that Labview FPGA does not support this module with the current version of NI-RIO, but I have the latest version of NI-RIO installed.
Solved!
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Hi RJ12,
Thank you for the info!
If this problem is holding you up you should give our Applications Engineering department a call at 866-275-6964 to discuss it. The 9076 can have some compilation compatibility issues with our motion modules so it's certainly possible you could be seeing such an error.
Feel free to get in touch with us if we can help out in any way, or consider starting a new thread with more details on the compilation error if you'd like to see if a corrective action report (CAR) already exists.
Best regards,
Andy C.
Applications Engineering
National Instruments

Similar Messages

Problems getting started with LabVIEW FPGA

Two (probably) related questions:
1. I am trying to get started with LabVIEW FPGA, and I am having trouble using a host VI to test my FPGA VI. I started with a basic QAM modulator VI, to be run on the FPGA, and I have reached the point where I need to verify the logic and timing with this VI running on the development computer with simulated IO. I have tried various combinations of putting the code inside single-cycle timed loops vs not; putting the modulator block directly into the host VI, and using the "FPGA reference" block. When neither the host VI nor the modulator VI use a single-cycle timed loop, I see correct behavior. In every other case, the output of the VI is either absent or incorrect. I need to use a single-cycle timed loop in the FPGA VI to properly verify timing behavior (as far as I know), so the one functioning case is not enough for me.
I'm sure there is a key step I'm missing or misunderstanding, but I have not been able to figure it out myself yet. I've attached my modulator diagram as well as two different attempts at host VIs. I can share other information, but I'm not sure what is most relevant.
2. I am also trying to test a simple wrapper VI for the Xilinx FFT block, and I am having trouble accessing FIFOs inside the host VI. I thought this would be relatively straightforward, but when I tried to change the "method" on an "invoke method" block, there were no options for accessing FIFOs, as I understood there should be. This is a total roadblock for me. These two diagrams are also attached, the test diagram shows the options available to me for the "invoke method" block.
Labview 2013, PXIe-7965R, PXIe-8133 controller.
I had to combine the diagram images; in case they are hard to follow this way, see the individual images here: http://imgur.com/a/oB6OD .
Thanks in advance for any suggestions.
Attachments:
mod_all.png ‏68 KB
fft_all.png ‏52 KB

Hello Monguin61
If you are having problems reading from DMA FIFO's you should test them using a very simple code to understand their behavior. First, you could start taking a look to the linked documents:
Reading DMA FIFOs from Host VIs (FPGA Interface)
Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices
FIFO.Read (Invoke Method)
Then you could test and analyze a simple example to understand how it works, for example this one: Simple DMA FIFO Example for FPGA.
Check the references when you are using DMA FIFO's, I noticed you did not connect them in the second picture attached.
Regards
Frank R.

RS 422 @ 8Mbit/s is it possible with Labview FPGA??

Hi,
I've to read and write data over an RS422 link at a rate of 8Mbit/s.
Do you think it's possible to implement RS422 @8Mbit/s with labview FPGA?
I know that I will have to make electrical adaptation to use RS422 signals with FPGA card.
Can the FPGA IP available on this website do this?
Thanks a lot
Julesjay

Christophe wrote "Yes it's possible to implement this into FPGA, if you adapt the electrical signal."
Are you sure ?
Depending on if that spec is baud vs bit rate and the over-sampling implemented in most serial read logic, the FPGA may not be able to cycle fast enough.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

HELP -FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA ?

HI EVERYBODY, IM TRYING TO USE MY FPGA BOARD WITH LABVIEW, BUT I DONT KNOW THAT IF ITS COMPATIBLE, I INSTALLED DRIVERS, FPGA MODULE, AND LABVIEW 2012, IM USING WINDOWS 7 32 BITS, AND AFTER I COMPILE ITS SAID :
LabVIEW FPGA called another software component, and that component returned the following error:
Error Code: -310601
NI-COBS: Unable to detect communication cable.
Please verify that the communication cable is plugged securely into your computer and target. Also verify that the appropriate drivers are installed.
THANK YOU .
=)
Solved!
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Hi dvaldez2.
LabVIEW FPGA does not offer support for any third party hardware, other than the Spartan 3E XUP Starter Kit. Those are probably the drivers you downloaded.
http://digital.ni.com/express.nsf/bycode/spartan3e?opendocument&lang=en&node=seminar_US
However, this driver only supports the Starter Kit board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=S3EBOARD). You can't use the driver with any other FPGA from Xilinx.
Hope this helps.
Aldo H
Ingenieria de Aplicaciones

LabVIEW FPGA PMW modulation for L298n H-bridge

Hello to everyone,
I am new in LabVIEW FPGA programing and I have a couple questions, so I would be grateful if you could answer me. For my final work I have to control the speed and direction of DC motor using sb-RIO 9636 and H-bridge L298n. In attachments you can find scheme of the H- bridge and my program. I have conected In1(pin 5 of L298n) to digital pin 1 of the card, In2(pin 7 of L298n) to digital pin 2 of the card and changing the state of the pin I change the direction of the motor(I know that the one In should be Low and the other High so the motor can rotate in one or the other direction). PWM(Enable pin of the L298n pin 6) I have conected to DIO3.
PWM signal I cretaed is shown in picture.
My questions are:
1.Will loop timer I used, provide that period of signal is lenght I specify in the control(for example if I put 20 000 will the period be 20000 s)?
2. Can I vary the duty cycle changing the control Waiting (DIO3 is HIGH for a couple of us, then it sets LOW, and then all that repeats )?
3. Earlier I thaugt that PWM signal I should send in both IN1 and IN2, and that the Enable pin is used to stop or start the motor. I tried that and the motor was rotating different speed, and I could stop or star the motor with enable pin, sending it HIGH OR LOW, but I could not change the direction of the motor. So my other option was to conect the pins as I explained at the begining. My question is: Should I PWM conect to the enable pin, and will thah work?
Thank you

I found a couple of resources that deal with PWM on the FPGA and motor control - they might be helpful to reference as you look for answers to your questions.
Developing a PWM Interface using LabVIEW FPGA
http://www.ni.com/white-paper/3254/en/
CompactRIO Motor Control Basics Tutorial
http://www.ni.com/pdf/labview/us/compactrio_motor_control_basics.pdf
PWM Output With LabVIEW FPGA
http://www.ni.com/example/26499/en/

C API version required for LabVIEW FPGA 2011

What is the verison of the C API that will work with LabVIEW FPGA 2011?
Solved!
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I would guess this one: http://www.ni.com/download/fpga-interface-c-api-2.0/2616/en/
The version numbers appear to start with years in 2012. This is the highest version I could find before 2012 and it was released in August of 2011. That time coincides with the annual NI Week festivities where a large portion of the software/hardware is released. It's a small download so it shouldn't be difficult to download and try it out.
But, you'll still need LabVIEW for FPGA development according to this white paper: http://www.ni.com/white-paper/9036/en/

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
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Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

Labview fpga module Spartan 6 LX9 FPGA

Does Spartan 6 LX9 FPGA supported in labview FPGA module ?

varunme,
The only FPGA targets that can be programmed with LabVIEW FPGA are National Instruments FPGA products (cRIO, sbRIO, R-Series, FlexRIO, etc) and the Xilinx Spartan 3E XUP board. Unfortunately, LabVIEW FPGA doesn't support third party devices containing the LX9 FPGA.
-Nick-
Nick C | Staff LabVIEW Platform Product Support Engineer | National Instruments

How to simulate external hardware in LabView FPGA ?

Hello,
I have a NI 7952R connected to a 6583 IO module.
This IO module is connected to a digital sensor that continuously sends patterned data.
I am developping the code for the FPGA and I would like to know how to perform a cycle accurate simulation of the whole system.
There is an example for a cycle accurate simulation of the labView -> FPGA interface, but it doesn't include the behavior of an external hardware connected to the FPGA IO module.
Now I have a VHDL simulation model (not synthetisable) that describes my sensor. How to include that into the iSim cycle accurate simulation?
Do I have to alter the 6583 IO module CLIP files by including my sensor description into it?

Thank you for your answer, I think now we have a common understanding of your intent.
Your I/O simulation model is integrated via a clip or ip integration node:
"In addition to VHDL code for the FPGA VI, you must provide simulation models for any IP you include through the CLIP and IP Integration Nodes. You specify the models for CLIP simulation and the IP Integration Node simulation through their configuration wizards."
Taken from:
Introduction to Cycle-Accurate Simulation
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_simulation_intro/

How can I access CAPI 2.0 methods with LabView ?

I must use CAPI 2.0 (common ISDN interface) method with LabView (graphical interface), the work is to command a ISDN S/T card on PXI Bus, and this card support CAPI 2.0.

This depends upon what type of interface you have to the ISDN. I assume you have either Basic Rate Interface (BRI) or Primary Rate Interface (PRI). Do you have a DLL to control it? If so, you can use the "Call Library Function Node" VI to access this DLL and just make calls to it. If you have an ActiveX Server, you can use the LabVIEW ActiveX Automation VIs to access it.
J.R. Allen

Qual a diferença do LabVIEW FPGA e o LabVIEW REAL- TIME?

Hello,
Could anyone help me? This question arose in my work and could not answer. Does anyone know tell me?
Thank you.
Solved!
Go to Solution.

Olá,
Com o LabVIEW FPGA você programa diretamente o chip FPGA presente no chassis cRIO, placas da NI Série R e single Board RIO. Você programa as E/S diretamente no chip, sendo assim uma programação de mais baixo nível. A grande vantagem do FPGA é o "paralelismo real", o que garante altas velocidades na execução das rotinas programadas.
Assista ao webcast Introduction to LabVIEW FPGA
Com o LabVIEW Real-Time você desenvolve aplicações que são críticas em relação a "tempo". Chamamos de aplicações "deterministicas". A idéia é que, se você tem uma rotina que deve ser executada em um tempo determinado, a diferença entre o tempo real e o que você programou seja o menor possível. Aplicações em Computadores comuns não são deterministicas, pois enquanto o LabVIEW executa uma certa rotina programada, o Windows está executando outras tarefas, monitorando a utilização de periféricos, atualizando a tela, etc.
Real time não significa "Velocidade", mas "Confiabilidade".
Assista ao webcast LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance
Hello,
With LabVIEW FPGA you program the FPGA chip itself. The FPGA chip is found into cRIO chassis, NI R-Series Boards, and NI Single board RIO. You program the I/O directly in the chip, so we consider this as a low level programing. The main FPGA advantage is the "Real Paralelism", which guarantees high speed execution programming.
Whatch Introduction to LabVIEW FPGA webcast
With LabVIEW Real-Time you develop called "time crictical" or "Deterministics" applications. In case of you routine must be executed in a specified period of time, the difference between the real time execution and the time you programmed is as low as possible. Commom computers programming are not deterministic, because in the meantime of executing a certain programmed routine, the OS (e.g. Windows) is running other appication tasks, monitoring peripherals like mouse and keyboard, uptading screen, etc.
Real-Time doesn't mean "faster" but "reliable".
Watch LabVIEW Real-Time: Graphical Development, Hard Real-Time Performance webcast
I hope the information helps you!
Best Regards
Felipe Flores
Engenharia de Aplicações
National Instruments Brasil

How to use LabVIEW FPGA on Custom FPGA board other than NI products .....Also how to develop RTx DLL for a customised motion controller hardware

I'm using RTx, LabVIEW RT and LabVIEW FPGA.
The GUI is windows based. The motion control and FPGA are RTx based.
Is there any way to develop device drivers for the custom hardware in RTx. For example motion controller hardware, FPGA hardware, PCI hardware.
Is there a possibility to use custom FPGA boards to use with LabVIEW FPGA.
Please send me some links
Thanks
Bhoopathy
Take life as it comes! you may never know what's gonna happen Tommorrow

CODE WARRIOR Hello. I believe this question was answered in a previous post. Please let us know if you have any new questioins or if you need some clarification.
You are able to develop device drivers for your custom hardware using the NI Measurement Hardware Driver Development Kit.
However, it is not possible to use custom FPGA boards with LabVIEW FPGA. The FPGA boards have to be one of our R Series boards. Here are some links that should shed some light on the Measurement Hardware DDK.
Measurement Hardware Driver Development Kit Frequently Asked Questions
NI Measurement Hardware DDK (Driver Development Kit)
Please post if you have further questios.
Efosa O.
NIAE

LabView fpga VHDL code and compiler

Hello,
I'm in the project where we would like to use NI hardware (more likely cRIO system). With NI hardware we will read/wright several AI/AO and DIO and perform some math and controls on the result of readings. We are planning to design FPGA code for project, but we are thinking about implement all data processing and control logic in VHDL and link it with AI, AO and DIO with help CLIP or IP Integration Node as explained in this : "white-paper": http://www.ni.com/white-paper/7444/en/
Mentioned above paper explain how to implement VHDL code in LabVIEW FPGA VI using CLIP or IP Integration Node, but the topic that is not highlight explicitly is how these construction CLIP and IP Integration Node will be handled by Compiler. The main reason for such approach (VHDL linked with part that read/write into hardware AI AO and DIO) we expect that our VHDL code will be handled by LabVIEW compiler without modification and passed to Xilinx Compiler synthesis as is (path for Compile process I've taken from here: http://www.ni.com/white-paper/9381/en/ ), so we will be able at some level bypass the intermediate process of compilation and get almost the same result as if we design pure VHDL code and use Xilinx ISE for Synthesis Mapping and Bit File generation.
Will this approach work? I was not able to find any documents that explain the Compiler behavior and confirm that VHDL code handled untouched or will modified, does such document exist?
Note. I've requested official assistance from NI support on topic above, but I would like to post this question on forum hoping get more feedback.

Hello RangerOne,
There won't be any modications to the internal logic of the VHDL that you implement in the IP integration node. Though I've seen developers unfamiliar with LabVIEW FPGA get tripped up on the synchronization registers that LabVIEW FPGA inserts into the code around the integration node. Learning where and why these syncrhonization registers are inserted has in my experience always resolved this issue. These two help documents do a good job of explaining the 'where and why' of synch registers when the enable chain is present, or when working with IO inside of a SCTL.
With regards to the stability of LabVIEW FPGA, I would second Daniel's sentiments. What about the known issues list conveys instability and risk? As a point of comparison, here are the known issues for ISE 14.x.
If you are looking to minimize risk, I would recommend developing the critical logic in the development enviroment in which you are comfortable setting up a comprehensive test bench since testing the code is the only way to truly verify its functionality. For me this would be LabVIEW FPGA as it has excellent trouble shooting tools and I've been developing in it for quite some time. Perhaps you're more familiar with ISE than LabVIEW FPGA and that is the source of your trepidation? If that is the case then you may find the High Performance FPGA Developers Guide a good read. You may also find a few of the case studies on our website reassuring since they demonstrate other teams successfully implementing a solution using LabVIEW FPGA. Here's one that used LabVIEW FPGA in conjnction with VHDL IP similiar to what you are doing.
National Instruments
FlexRIO Product Support Engineer

Windows 7 Compatability with Labview 8.0 and missing files while interfacing the FPGA with LV

I am trying to use an FPGA (PCI-7830R) with Labview 8.0. The computer has Windows 7 OS. I installed LV 8.0 in the proper order with the FPGA Module and labview is able to see the FPGA when I open a .lvproj (the FPGA is in the tree) however there is a warning symbol next to the FPGA selection and when I try to open a .vi file that is used on the other stations in my lab (it works on all the other stations), labview is unable to find a whole bunch of files. There are some pictures.
Missing File (there are a bunch more but this is the fist one).

According to this LabVIEW Compatibility LabVIEW 8.0 is NOT compatible with Windows 7
Visualize the Solution
CLA
LabVIEW, LabVIEW FPGA

FPGA Interface between Simulink/Matlab und Labview

Hello People,
I has a diploma topic, where I must call a Fpga I/O (AI/O or DI/O) from a block in Simulink(Simulink Model) . I can make the programming of the Fpga on ni pxi 7813R under labview . Around a Simulink model with Labview to connect one needs SIT.
Now the question:I can define the I/O of the Simulink Model under labview , now I must the I/O in Matlab/Simulink in block set define . White someone any information about it, I white not yet as I know that realize please to say her me each information me to help can.
Thanks very much
houssa

Hello FourtwonaFirst thanks for your answer and your interest, I try to explain what i want to realize. I have a Model in Simulink, I can this Model connect in LabVIEW with simulation interface toolkit, and with SIT Connection manager the hardware I/O as Model I/O configure.
I would like to make the I/O interfaces of a FPGA 7813R PXI system from Simulink accessible. Similarly as with dSPACE RTI block, I can access the I/O from Simulink means over S Function Block. for example Analog Input.
Also I want to define the I/O of the Model as FPGA I/O in Simulink and then can I build the ModelDLL in Matlab and in SIT download. finally run the Model-simulation on RT Target.
I think, we need access to the visa server. I am on the search for this concept.
Perhaps you or someone can support me.
My Regards and thanks
HooSSa

NI 9512 with Labview FPGA Interface

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