Questions about the load processing of OpenSparc T1 Dcache

Hi,
I have some questions about OpenSparc T1 Dcache load processing.
During load processing, subsequent loads to the same address need to search the store buffer for a valid store to that address. If there is a CAM hit, data is sourced from the store buffer, not from the D-cache, and no load request will be sent to the L2.
What if there is no CAM hit. Would the load request be sent to L2? Or would Dcache be checked for the requested data?
If the load request would be sent to L2, what next? Would the Dcache be updated?
Thanks

Store buffer is checked for Read after Write (RAW) condition on loads. If there is full RAW - i.e. full data exists in the store buffer - then the data is bypassed and no D cache access happens.
If RAW is partial (e.g. word store followed by a double word load) then load is treated as a miss. Store is allowed to complete in L2 cache and then load instruction is completed.
For the miss in STB, D cache is accessed. If hit, data is fetched from D$. If miss, data is fetched from L2$ and allocated in D$.

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