Repeatedly Changing AXI BAR 0 Address Register but Microblaze Keeps Reading from the Same Address

Question

Hello,
I work on a project based on AXI PCIe Bridge.
What I am trying to do is access a userspace memory block directly from a Microblaze (or DMA).
So far, I use posix_memalign() to allocate a block of memory in the userspace which has the size of the page (4K).
Once I allocate this block of memory I fill it with data.
Then I pass its pointer to my kernel driver where I use get_user_pages() and a few other functions to create a scatter/gather list in order to get the physical addresses of my userspace pages (so far I get one physical address since I have allocated one page).
The next step is to write that physical address to the AXI BAR 0 address register.
I validate that the correct address is written at this register.
Then I ask the Microblaze to read the data from this physical address but I get different data.
After reading the data I ask the Microblaze to write new ones at this address.
I repeat all that procedure by allocating new memory block filled with different data in my userspace.
Then I pass the new physical address again at the AXI BAR 0 address register.
This time the Microblaze reads the last data it wrote itself.
It seems like the Microblaze always reads/writes from/to an unknown address even if I repeatedly give different physical address at the AXI BAR 0 address register.
Are there any suggestions?
Could this be a cache coherency issue?
Trying the "cache coherency issue" approach, though, did not solve the problem either.
I have, also, tried a different case which worked.
I used pci_alloc_consistent() in my kernel driver and I gave its physical address to the AXI BAR 0 address register.
Then the MIcroblaze writes and reads data from/to this block of memory correctly.
The kernel driver verified that the transfers are correct since it read the same data that the Microblaze previously wrote.
This approach always worked for every new allocated block of memory.
 

Answer 1

Hello,
I work on a project based on AXI PCIe Bridge.
What I am trying to do is access a userspace memory block directly from a Microblaze (or DMA).
So far, I use posix_memalign() to allocate a block of memory in the userspace which has the size of the page (4K).
Once I allocate this block of memory I fill it with data.
Then I pass its pointer to my kernel driver where I use get_user_pages() and a few other functions to create a scatter/gather list in order to get the physical addresses of my userspace pages (so far I get one physical address since I have allocated one page).
The next step is to write that physical address to the AXI BAR 0 address register.
I validate that the correct address is written at this register.
Then I ask the Microblaze to read the data from this physical address but I get different data.
After reading the data I ask the Microblaze to write new ones at this address.
I repeat all that procedure by allocating new memory block filled with different data in my userspace.
Then I pass the new physical address again at the AXI BAR 0 address register.
This time the Microblaze reads the last data it wrote itself.
It seems like the Microblaze always reads/writes from/to an unknown address even if I repeatedly give different physical address at the AXI BAR 0 address register.
Are there any suggestions?
Could this be a cache coherency issue?
Trying the "cache coherency issue" approach, though, did not solve the problem either.
I have, also, tried a different case which worked.
I used pci_alloc_consistent() in my kernel driver and I gave its physical address to the AXI BAR 0 address register.
Then the MIcroblaze writes and reads data from/to this block of memory correctly.
The kernel driver verified that the transfers are correct since it read the same data that the Microblaze previously wrote.
This approach always worked for every new allocated block of memory.