The compilation failed due to a Xilinx error (410)

Hi Peeps,
I'm trying to compile my FPGA code with the Cloud Compile Service. I have an FPGA code that compiles without any problems. When I put a DMA FIFO Node into this code, I get the following Xilinx compiler error:
ERROR:HDLCompiler:410 - "/opt/apps/NIFPGA/jobs/CSD2awO_GQdD63p/NiFpgaAG_0000050c_CaseStructureFrame_0001.vhd" Line 211: Expression has 66 elements ; expected 50
Netlist NiFpgaAG_0000050c_CaseStructureFrame_0001(vhdl_labview) remains a blackbox, due to errors in its contents
The code compiles well without the DMA Node. The DMA is a Target to Host DMA, 1023 element long (Block Memory), the type of the elements is U32.
There are other thing on the block diagram as well. When I copy this SCTL into a new VI without anything else in it, it compiles without problems, regardless if the DMA Node is there.
Please find the VI snippet and the error summary attached.
Any ideas are welcome.
Cheers,
Norbert
Solved!
Go to Solution.
Attachments:
FPGA.png ‏92 KB
Error Report.txt ‏36 KB

So the problem seems to be resolved...
I deleted the DMA FIFO node from the block diagram and added it again. After about 40 minutes I had a successful compilation. Weird.

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LabVIEW FPGA: The compilation failed due to a xilinx error

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-->
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Date results were retrieved: 2014/2/26 18:17
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Solved!
Go to Solution.

I have got the same error, Have you solved this error?
What you have done?
jasonneu wrote:
I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
Details:
ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
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Compilation failed due to a Xilinx error

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Compilation failed due to timing violations, Getting Xflow error and resources over use.

Hi,
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