Welcome to Hierarchical Design - Design Preservation and Partial Reconfiguration

Question

Welcome to the Xilinx Hierarchical Design Forum.  This is the forum for all of your Design Preservation and Partial Reconfiguration questions.    
The major goal of Design Preservation is to reduce the number of synthesis and implementation iterations during the timing closure phase.  This is accomplished by using previous implementation results for unchanged portions of the design.
The major goal of Partial Reconfiguration is to allow a portion of the design to be reconfigured while the rest of the design is still running in the FPGA.   Different configurations of the design can be swapped back and forth reducing overall design size and power.
For more information on the Design Preservation flow please see:
White Paper - Repeatable Results with Design Preservation
Hierarchical Design Methodology Guide
PlanAhead_Tutorial_Design_Preservation
Leveraging Design Preservation for Predictable Results Video
For more information on the Partial Reconfiguration flow please see:
Partial Reconfiguration Website 
Partial Reconfiguration User Guide
Partial Reconfigurations using PlanAhead Video
This forum is monitored by several Xilinx employees.  Please feel free to ask any questions.
 

Answer 1

Hello, I am trying to modify the Hierarchical Design tutorial TCL example (design.tcl) to allow me to adapt it to a simple trial project using the HD flow. At the Viavdo 2013.4 Shell when i type in:
vivado -mode batch -source design.tcl -notrace
I keep seeing these ERRORS from Vivado :
# Vivado v2013.4 (64-bit)
# SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
# IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
# Start of session at: Thu Mar 06 09:25:31 2014
# Process ID: 5200
# Log file: C:/GoldenHD_Tutorial/Vivado_Tutorial_TD/vivado.log
# Journal file: C:/GoldenHD_Tutorial/Vivado_Tutorial_TD\vivado.jou
Attempting to get a license: Implementation
Feature available: Implementation
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source design.tcl -notrace
#HD: Setting Tcl Params:
    place.closeImportedSites == 1
    tcl.notrace == 1
    hd.visual == 0
#HD: Running synthesis for block HD_trig_detector
    Writing results to: ./Synth/HD_trig_detector
#HD: Writing checkpoint ./Synth/HD_trig_detector/create_project_error.dcp for debug.
ERROR: [Common 17-53] User Exception: No open project. Please create or open a project before executing this command.
ERROR: write_checkpoint command failed.
    write_checkpoint -force ./Synth/HD_trig_detector/create_project_error.dcp
    while executing
"error $errMsg"
    (procedure "command" line 31)
    invoked from within
"command "write_checkpoint -force ${logName}_error.dcp""
    (procedure "command" line 23)
    invoked from within
"command "create_project -in_memory -part $part" "$resultDir/create_project.log""
    (procedure "synth" line 36)
    invoked from within
"synth $module"
    ("foreach" body line 5)
    invoked from within
"foreach module $modules {
      if {[get_module_attribute $module synth]} {
       puts $rfh "\n#HD: Running synthesis for block $module"
       comma..."
    invoked from within
"if {[llength $modules] > 0} {
   foreach module $modules {
      if {[get_module_attribute $module synth]} {
       puts $rfh "\n#HD: Running synthesi..."
    (file "./Tcl/run.tcl" line 29)
    while executing
"source $tclDir/run.tcl"
    (file "design.tcl" line 131)
INFO: [Common 17-206] Exiting Vivado at Thu Mar 06 09:25:48 2014...
This seems weird...why is Viavdo issuing errors about not having an open project when in HD mode it is running in non project mode ?
Can anybody help me diagnoise the route cause of this problem please ?
many thanks for any help i get,
i have attached my design.tcl file to this query :)
Dr Barry Henderson