About implement problem by ISE 14.5 & SPARTAN SP-605

Hi, I want to implement the amber23 core(it is post on opencores.org and it was verificated) on Spartan 6, SP-605.
Therefore, I use the ISE 14.5 webpack version.
The user guide said it can be implemented. I implemented the amber23
and set the top module as 'system.v' and open all sources in the hw/vlog,
but the compile result is
INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
Therefore, search about this error, and change the process properties like
opt_mode, opt_level, keep-hierarchy, read_cores, use_dsp48, equivalent register removal,
-use_new_parser yes ...
but it doesn't work...
and remove related with the ddr3.v, because I don't need it and there's no file about ddr3.v in amber prj, but the error was not dissapear...
Please help me to implement the prj
or if you have the ISE project file that you already done by the a23 core, please talk to me
Thank you

Uhm,
opencores can be great for sources, but the bigger designs can be a big step if they work first time.
IN fact just like most IP I have ever purchased, its just wth IP u pay for at least you can shout at some one, it still might not get the IP working, but hey. 
So this looks like a pure Xiiinx error report, being reported in the Xilinx Xst:cmain.c 
but that does not mean ints a xilinx bug, it just means the tools did not understand something in the source code, and bombed out with a not very usefull error message.
welcome to the fun.
So if the tool does not give you an clue, nore the IP, then its down to divide and conquore .
I assume the project is made up of many smaller files, with one as top, and you have a fair undrstanding of the RTL process.
So , try start cutting the project up, by making various second level files 'top', and re compiling .
    that should enable you to localise where the problme is.
Have fun,

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