Apply VCCO at 3.3V before VCCINT will damage the chip?
Hi;
I saw in the datasheet of Artix-7, the right power sequence is VCCINT, VCCBRAM, VCCAUX, VCCO. My question is if this sequence is violated, that is, if I supply VCCO before VCCINT and other powers, will the chip be damaged?
We are developing a new PCB which has a A7-200T on it, and we found the chip was damaged, we are trouble-shooting.
Please help!
Donald
Hi,
I'm facing similar (I think) problems with Artix-7. Our design has an ADC with CMOS (LVCMOS25) outputs interfacing with Artix-7 XC7A200T (FFG1156) through CMOS buffers. Our ADC is 16 bits, 130 MSPs connected to User I/O pins of the same bank. By some reason some of the user I/O pins of the FPGA that interfaces with digitized data pins of the ADC are damaged. We have produced 6 FPGA boards and 4 of them presented problems on the same pins. We have identified that:
- The clamping diodes of the damaged user I/O pins are working well (I have measured it)
- The FPGA configuration is correctly set for LVCMOS25 and pull-up
- Even when setting the input voltage as logic level "0" on the damaged user i/o pins, I always read logic level 1
- The power-up/down sequence for VCCO and VCCaux is ok and the voltage levels are well beyond 2.625 Volts during TVCCO2VCCAUX
- All the input voltages of the user i/o pins are well within the limit of 0 Volts and 2.5 Volts. Even in the case of driving the inputs with high voltages, peak voltages driven by CMOS buffers cannot provide enough current to damage the input buffer due to the fact that the clamping diodes will protect the i/o (remember I said that the damaged pins have clamping diodes working well)
- I have already set the damaged user I/O pins as input, output, pull-up, pull-down, different voltage levels, but they are not working and are always set to logic level "1".
Questions:
- Do you have a suggestion on what can cause damage to the user i/o pins considering that I have 16 identical LVCMOS25 inputs and 2 of them are by some reason being damaged?
- Can I have access to the user i/o pin electrical scheme?
- Can grounding problems damage user io pins?
- Has anyone reported similar problems?
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