Artix 7 GTP clock

Hi
when looking at the Differential voltage needed at the Clock In for the GTP, we can see 350mV minimum.
On Spartan 6 for exemple, that ViDiff min was less : 200mV.
We want to be sure that there is no error in the data sheet because it is very different from previous version of GTP and also VIdiff for differential RX in GTP also.
Thank you
Caroline

c,
The data sheet is accurate. Once a device is in production, all numbers are valid. 350 mV p-p is the minimum acceptable value.
If there is a number that is incorrect, the data sheet is changed, and the revision history denotes that.
Errata may be applied before production, in which case you need only review any errata that apply.

Similar Messages

How to use a pll output to drive the clock input?

when i use the following code to generate a clock（CLK00IN) from MHZIN to drive the normal logic,it work normally,but when i use it to drive the gtp clock input port CLK00,CLK00IN become 0 (no signal),why?
IBUFG system_clk_ibufg
.O                              (sys_tile0_gtpclkout0_0_to_cmt_i),
.I                              (MHZIN)
PLL_BASE #
         .CLKFBOUT_MULT     (10),
         .DIVCLK_DIVIDE     (1),
         .CLK_FEEDBACK      ("CLKFBOUT"),
         .CLKFBOUT_PHASE    (0),
         .COMPENSATION      ("SYSTEM_SYNCHRONOUS"),
         .CLKIN_PERIOD     (25.0),
         .CLKOUT0_DIVIDE    (5),
         .CLKOUT0_PHASE     (0)
    system_clk_pll
         .CLKIN             (sys_tile0_gtpclkout0_0_to_cmt_i),
         .CLKFBIN           (CLK00FB),
         .CLKOUT0           (CLK00OUT),
         .CLKOUT1           (),
         .CLKOUT2           (),
         .CLKOUT3           (),
         .CLKOUT4           (),
         .CLKOUT5           (),
         .CLKFBOUT          (CLK00FB),
         .LOCKED            (),
         .RST               (system_clk_pll_reset_i)
    BUFG sys_clkout0_bufg_i
        .O              (CLK00IN),
        .I              (CLK00OUT)
    );

Whether this experiment is done for test purposes?
GT should not have any impact on CLK00IN signal in the code here. GT comes into picture after sys_clkout0_bufg_i. Please check if any optimization happened during implementation.

Artix 7 GTP issues weak rxresetdone signal

Hi,
I am using vivado 2015.2 and GTP/gigabit ethernet CC protocol. The example design is simulated correctly with 'rxresetdone' is asserted. But in AC701 Eval board, the rxresetdone signal is not asserted.
'txresetdone' is asserted even the "SOFT_RESET_TX_IN" input is asserted. Strange?
Anyone had experience with this?
Thanks,
ezhangq

After tied data_valid_in to '1', 'rxresetdone' is asserted correctly. Thanks.
Now in my application, I will use the internal PRBS check. Should 'data_valid_in' be always tied to '1' in this case?

Problem about link status in IBERT GTP

hI?
I use a artix xc7a75t-fgg676 wih vivado 2015.2 and revision IBER = 3.0(rev8).
This fpga have 2 GTP quad in bank 216 and 213. I use two gtp
With IBERT the GTP Bank213 work well at 3.125GBPS
but the GTP in bank 216 work (status) only at 0.625GBPS
The two GTP have each a hardawre clock of 156.25MHz.
This value is correct when i measured it with my oscilloscope.
We can see the configuration of the IBERT in picture 1,2 and 3
And the result, in picture 4.
Is someone have already seen this problem.

The formula from the ug482 user guide gives the lina rate as:
fPLLclkOUT = fPLLclkIN*(PLLx_FBDIV *  PLLx_FBDIV_45)/ PLLx_REFCLK_DIV
fLineRate = fPLLclkOUT *2/ RXOUT_DIV
I have checked my xdc and is good
fPLLclkIN                    = 156.25MHz
PLLx_FBDIV       = 4
PLLx_FBDIV_45    = 5
PLL0_REFCLK_DIV = 1
RXOUT_DIV                = 2
fPLLclkOUT = 156.25*(4*5)/1 = 3125MHz
fLineRate     = 3125 * 2 / 2 = 3125MHz
so parameter in xdc is good
Someone can help me?

Can't simulate Clocking Wizard in ISE 14.7

Hi!
I have developed a simple design for a VGA module where I need to produce a 40Mhz clock out of 100Mhz input for an Artix-7 (XC7A100T-CSG324) on an Digilent Nexys4 evaluation board. In order to aquire this clock I have used a Clock Wizard for a DCM. I have synthesise the desing, upload the bit file and everything works fine, as expected on the board.
I would like to extend the design and add more functionality. I order to achieve this, I need a test bench in parallel that will help me to continue the work. I have started by implementing the simplest test bech just to make sure it works. iSim doesn't want to start and the errors suggests that it doesn't see all the ports of the DCM:
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 131: Module <DCM_default> does not have a port named <CLK_IN1>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 133: Module <DCM_default> does not have a port named <CLK_OUT1>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 134: Module <DCM_default> does not have a port named <CLK_OUT2>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 136: Module <DCM_default> does not have a port named <RESET>.
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
I don't understand what I'm doing wrong...the same code synthesize and produce succesfully the bit file and everything works fine but I can't simulate it. I'm using ISE WebPACK Design 14.7 (P.20131013).
My test bench:
module VGA_top_tb(
reg clk = 1'b0;
reg reset = 1'b0;
initial begin
#5 reset = 1;
#30 reset = 0;
end
always begin
#5 clk = !clk;
end
VGA_top VGA_DUT(
//inputs
.clk (clk),
.reset_h (reset),
.up_btn (1'b0),
.down_btn (1'b0),
.left_btn (1'b0),
.right_btn (1'b0),
//outputs
.red (),
.blue (),
.green (),
.hs (),
.vs ()
endmodule
DCM code:
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "DCM,clk_wiz_v3_6,{component_name=DCM,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module DCM
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
// Input buffering
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (20),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (20),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (50),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (LOCKED),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
endmodule
Thanks!

Hi Gabor!
Thanks for your reply. I have noticed your observation that the naming of the DCM is different in the error message. I have re-name it before I post it in here but nothing changed. I have also tried "re-run all" to start the simulation but with no success.
In the end, I have manually removed the DCM instance and created a new one with the same parameters. This seems to solve the issue. Now works both on the board and in simulations. I'm not entirely sure what was the problem in order to avoid it next time.
Thanks for your help!

MIG clock frequency configuration

Dear All,
I have a question. I am generating MIG in VIVADO 2014.1 and I want to have clock period equal to 1250 ps which is generating clock with 800 MHZ for my SODIMM but I want to have memory controller work with 400 MHZ which means that PHY to controller clock ratio should be 2 but it does not have this option and it can be JUST 4 (it is disable and automatically it is selected as 4).
I know it might be different than standard but the question is that is there any way to have MIG which works with 800 MHZ SODIMM and has memory controller working with 400 MHZ.
I was thinking to generate MIG with clock period = 400 MHZ but choose PHY to controller clock ratio = 2 then when it is generated then I can change the parameters of PLL to generate 800 MHZ instead of 400 MHZ.
if it is not recommended what else I can do ?
thanks for your prompt reply in advance,
Meysam

Meysam -
The Zynq Kintex-7 PL fabric is pretty fast, but asking a complicated memory controller and whatever logic interfaces with it to run at 400MHz is asking too much. The tool won't let you select 2:1 for that reason. You're going to have to either compromise on speed or on data width. Depending on PL fabric (Artix or Kintex) and speed grade, 400MHz is near or even beyond the maximum frequency for hard resources like block RAMs and DSP blocks (see data sheet). That's a good indication that you can't do much at that clock rate.
Having a data path 512 bits wide is a little unwieldy, but the nice part is that this width matches the 64-byte burst size at the SODIMM. This simplifies your interface with the controller somewhat. If you really need 800MHz at the memory I don't think you have any choice.
Good luck.

Difference between slice and tile Artix 7

Hello, here I attached a pic of a part of my FPGA (Artix 7 ac701).
From this pic I can understand that there are 10 slices, where each of these is recognized by XY coordinates. A tile is a division that includes sites, wires and PIPs. My question is: Is a tile contained into a slice? Meaning that a slice contains many tiles.
Thanks

These are clock regions not the slices. Check the user guide page no 28 for more info
http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Is there a way that iTunes can act as a Radio Alarm Clock? I have found the radio station I enjoy listening to in the iTunes Radio List. Is there anyway iTunes (and my Mac) can be set to come-on and start playing that Radio Station from Sleep mode at spec

Is there a way that iTunes can act as a Radio Alarm Clock?
I have found the radio station I enjoy listening to in the iTunes Radio List. Is there anyway iTunes (and my Mac) can be set to come-on from Sleep mode and start playing that Radio Station at specific times of the day?
Any App or plug-in that does that?
Many thanks
Kevin

Turning your Mac into a clock radio.
1. In iTunes create a playlist that contains just the radio station you want to wake up to.
2. Export the playlist (as .m3u works well). Get Info on your playlist file and look at the Open With entry to make sure it points to iTunes, VLC or some other app that will stream your station.
3. In iCal create an event entry at the time you want to wake up.
4. Right (or Control) click on your wakeup event and select Get Info.
5. For "alarm" select Open File.
6. Now under Open File there will be a place to add the file to open. It will probably be some default entry (like iCal). Click on it will allow you to select "other." Then use the file dialog to select your playlist file.
Your Mac will wake you up at the appointed time. You don't need to keep iCal running. If you want to put you Mac to sleep for the night then there is one more thing you need to do. Open System Preferences to Energy Saver and click on the Schedule button. Check Start up or wake and set the wake up time to slightly before your iCal alarm time.
Dan

Adobe Extension Manager CC spins forever (shows the clock)

My Adobe Extension Manager CC spins forever and doesn't load properly with a continuous clock.
After a while I have to manually force quit the app in order to close it.
I tried to uninstall and reinstall it and it still hanging.
Please advise as this is a known issue for the past year or two and it seems you guys haven't pushed a fix.
I am running on a Mac, thanks.

Please try to run EM as administrator firstly.
1. Run "/Applications/Utilities/Terminal.app".
2. Input the following command then press "Return" key. Don't miss the double quotation marks.
   sudo "/Applications/Adobe Extension Manager CC/Adobe Extension Manager CC.app/Contents/MacOS/Adobe Extension Manager CC"
3. Input password of administrative user then press "Return" key.
If it works, you can try to run EM in normal way.
If it doesn't work, please run "/Applications/Utilities/Disk Utility.app", select your hard drive then repair disk permissions.
If it still doesn't work, please generate log files and send it to [email protected]
1. In Terminal window, run the following commands in turn:
   cd ~/Library/Application\ Support/Adobe/Extension\ Manager\ CC/
   mkdir Log
   cd Log
   touch ExManCoreLibLog.YES
2. Open Finder, hold down "option" key, click menu "Go"->"Library" to go into hidden Library folder, then go to its subfolder "Application Support/Adobe/Extension Manager CC/Log", check whether file ExManCoreLibLog.YES exists.
3. Launch EM.
4. After EM hangs, force quit it, send all the files in the Log folder above to us.

My iPhone 4 no longer connects to my car or alarm clock after a recent sync to my computer. The message at I get when trying to. Connect is "this accessory is not optimized for the device" or something like that. Anyone know how to fix this?

My iPhone 4 no longer connects to my car or alarm clock after a recent sync to my computer. The message at I get when trying to. Connect is "this accessory is not optimized for the device" or something like that. Anyone know how to fix this?

Hello there philp_69,
If I understand correctly it sounds like your phone hasnt been recognized in iTunes on your PC since the last couple of updates. I would use the troubleshooting in the following article which will walk you through the steps one by one.
iPhone, iPad, or iPod touch not recognized in iTunes for Windows
Thank you for using Apple Support Communities.
All the very best,
Sterling

Computer clock resets to 1969. PRAM battery probably not the issue.

I have a PowerMac G4 mirrored doors computer running Tiger 10.4.11 that occasionally starts up with that error message saying: "Your computer's clock is set to a date before March 24th, 2001. This may cause some applications to behave erratically."
I know all about resetting the PRAM, resetting the NVRAM, and replacing a weak, or expired battery. I've read the relevant posts on the subject, in which well-intentioned guides say that the problem is "usually" or "generally" related to the PRAM battery. Well, I wish it could be that simple, because I have already had a new battery installed, and the problem continues. It is intermittent; it's been occurring for about six months now; and it persists.
I seek technical assistance and successful, problem-solving suggestions that go beyond merely suggesting that I zap the PRAM or replace the battery.
If there are potential SOFTWARE problems, please direct me to those potentially damaged files. None of the disk utilities that I have used—including Disk Warrior, TechTool Pro, OnyX, Cocktail, or Drive Genius— find anything wrong with my hard drive or the files on it. No corrupted resources are reported. Additionally, Intego's Virus Barrier finds no infected files either.
However, a FileBuddy search of files modified before 3/25/2001 finds several dozen files with improbable dates of 12/31/1969 or 1/1/1970. Fewer files dated 12/31/1969 occur after I go to the Date/Time preferences pane and reset the clock to the current date/time and then restart my computer, especially in regards to system-related files. Nonetheless, several dozen files with a 12/31/1969 still remain, even after the date/time reset and the system restart.
I do not know if any of those pre-historic files are playing a role in this chronic problem, so I offer that information for the technically more astute to ponder upon and factor in to any solutions which might be offered. I have read posts where someone might suggest a re-install of Tiger, but the original poster almost always reports that re-installing Tiger did not eliminate problem, so I would prefer suggestions that rely on a scalpel rather than a sledge hammer.
If someone suspects that there may be hardware problem, I would like to hear theories along that line, too, although I am unlikely to consider gutting the hardware items just to retain the attractive computer case. Even though I do have other computers (an iMac G5 and a MacBook Pro), the PowerMac G4 is my preferred workhorse, and it is the only one configured to run Final Cut Pro (version 4.5; I can't afford to upgrade now), so I want to keep it functional without a major investment into an older machine.
When the computer clock problem first reared its irritating head several months ago, it was accompanied with kernel crashes that turned out to be related to the nVidia video card. I brought the machine in to a local shop, because it was refusing to power on. They installed a new battery to replace the original, probably weak original battery, and they replaced the probably defective nVidia video card with a used nVidia card I found on eBay. The shop also claimed that I needed to replace the motherboard and the power supply to ensure that the G4 would power on and that it would present a desktop without the warning message about the computer clock being set to 12/31/1969.
I decided to reject their assessment, since the whole repair job would have amounted to about $1,100. It seemed like an excessive solution. Since taking the G4 back about three months ago with only the new battery and the replacement video card installed, the computer has powered on every single time without fail, which, to my non-technician mind, would appear to indicate that the power supply is OK. However, I do still get an occasional warning about the computer clock being set to a date before March 24th, 2001.
I do not have the technical expertise or repair knowledge to know if the problem is hardware-related, software-related, power supply-related, or a complex interaction between all of them. If someone can suggest a permanent fix to eliminate the computer clock error problem WITHOUT requiring me to make a major investment in repairing or replacing hardware components, that would be ideal. On the other hand, if this clock problem is merely is an irritant, but not a sign of something more serious or expensive, then I am willing to live with it and get around the problem by going through the steps of resetting the clock when required and then restarting the computer with a correctly set clock.
My main goal, of course, is to have a reliable, stable computer. If it costs too much to eliminate the computer clock irritation on a permanent basis, then I am willing to live with the problem, as long as its presence does not disrupt my work flow. In that case, I would appreciate it if someone could explain what might be going on, so that I know what to expect and what to do about it.
I hope this is sufficient information with which to make a diagnosis and recommendation. If not, ask for more. Thanks.
bowlerboy

Short answer =
5) Upon reboot after re-connection and re-start, the Date & Time shows...
a) in the Date & Time pane: 12/31/1969 at 7:00 PM, and counting
b) in the Finder's menu bar: 7:00 PM, and counting
What do the results of this test tell you? Is this a software or a hardware problem?
======================================================================
Long answer =
Thanks, BDAqua, for offering your help. I'm not exactly new to these forums, but somehow my previous contributions have all been wiped out, so I've restarted under a new account name.
I've had my G4 MDD for five years, and it's always been quite stable for me, so I'm not quite sure that this model is "cantankerous." I do find the computer clock error message irritating, though, so it would be nice to know the source of the problem and its permanent solution.
Since my original posting, I elected not to Shut Down the G4 to see what would happen. It functioned just fine since then, allowing me to create some short Final Cut Pro movies as Christmas presents to family members. With one exception, all other applications also functioned without problems. The only problem I'm encountering has to do with H-P Photosmart Studio, an application bundled with the HP All-in-one model C7280. It will not settle down to work, forcing me to Force Quit it every time. Since that app works fine on my iMac G5, I decided to trouble-shoot it by reinstalling the HP software, a process that requires me to Shut Down. (If possible, I want to see if the problem is with the HP software, or with Tiger on my G4.)
However, before I can get even get to trouble-shooting the HP Photosmart, the G4 gives me that computer clock error upon re-boot. In the past, the Date & Time error message has appeared upon a cold reboot, no matter whether I had reset the Date & Time in the preference pane via the Network clock or manually. However, I never conducted my tests in conjunction with disconnecting the A/C power cable. So, I decided to try the the test you suggested. Here are my observations and the results of the test.
1) Upon Shut Down, cool down, and restart, I get the computer clock error message mentioned at the beginning of my original post, telling me that my clock is set to a earlier date.
2) When I open the Date & Time preferences pane, however, the date and time shown there (as well as on the Finder's menu bar) is current.
3) The Network setting was ON, so, to comply with this test, I unchecked the "Set date & time automatically" box. I do not need to reset date and time manually, because, as I mentioned they ARE set correctly, even though the message I got upon restart said that they are not. (If memory serves me correctly, though, the Date & Time panel would actually show 12/31/69 as the computer clock's read-out, so this discrepancy is somehow connected to this problem. )
4) I shut down the G4 for 2 hours, and I disconnected all cables and plugs to it, including A/C power.
5) Upon reboot after re-connection and re-start, the Date & Time shows...
a) in the Date & Time pane: 12/31/1969 at 7:00 PM, and counting
b) in the Finder's menu bar: 7:00 PM, and counting.
6) I take screen captures of the error message and the menu bar: both .PNG files are time-stamped as of 12/31/1969 at around 7:01 PM.
7) I will now reset the clock to the current Date and Time by turning the Network time feature back on, so I can get on with my work while the trouble-shooting process continues.
What do the results of this test tell you? Is this a software or a hardware problem?
If it's a software problem, then should I do I clean install of Tiger? If I do that, is there any evidence that a clean install will do any good to eradicate the problem?
On the other hand, if this is a hardware issue, is it contained to merely being an irritant that I can fix merely by adjusting the Date & Time whenever the problem occurs (which I can live with, as long as the system is stable after that fix), or is this error message regarding a sign of something more ominous failing on the motherboard?
bowlerboy

Is Mail.app one of the "erratic" behavior apps with a reset system clock?

I am hoping someone can help with a fine detail of mail.app (v2.1.3) behavior.
I had an incident where an iMac sent out 200+ smtp hits a minute and was tossed of the network for presumed zombie spaming.
I think I have actually tracked the problem to an unfortunate conjunction of circumstances that is actually innocent (if still annoying)
Let me set up the story:
1. This is a common use computer, so Mail is not configured (except that it is --I'll get to that in a moment) and
2. Safari will invoke Mail when you click on an "email link"
Mostly everyone just quits mail if they goof and click an email link.
BUT some time ago at least one person invoked Mail and composed a message. This message, naturally, remained in the outbox ever since. That person learned that they can't send email that way, so ever since they just cmd-Q Mail.
BUT Before this person learned, they walked through the mail-config and told mail to try hitting smtp.mac.com:"nonExistantUser".
So that covers the lead-up. Two days ago, mail was invoked via a Safari link, BUT it wasn't quit, it was sent to the background.
Where it undoubtedly tried to send the outbox repeatedly until it was kicked off the network.
Here is what I don't understand:
Under this scenario of a mis-configured .mac address, will mail repeatedly try and fail to smtp at the maximum possible rate?
OR
Is the one other factor I am about to describe responsible?
The one other factor:
The clock battery is dead and there was a power failure at 4am that day.
The system clock reset to 1969.
Of course, nobody reset it.
Is mail.app one of the apps that the finder message warns "may behave erratically"?
(a GROSS simplification) does it have a bit of code like:
1 check time-of-last-send-mail-attempt
check newest-item-in-outbox
if newest-item more recent then last-send-attempt
do send-mail and record time-of-last-send-mail-attempt
and go to 1
else wait X minutes and go to 1
which, if the clock was mis-set to 1969 would always record a last-send-attempt prior to anything in the outbox and trigger a send loop.
Does anyone know if either Mail is tenacious about sending to a bad .mac address, or gets ridiculous under this circumstance for bad-clock-set?
Marc

I am hoping someone can help with a fine detail of mail.app (v2.1.3) behavior.
I had an incident where an iMac sent out 200+ smtp hits a minute and was tossed of the network for presumed zombie spaming.
I think I have actually tracked the problem to an unfortunate conjunction of circumstances that is actually innocent (if still annoying)
Let me set up the story:
1. This is a common use computer, so Mail is not configured (except that it is --I'll get to that in a moment) and
2. Safari will invoke Mail when you click on an "email link"
Mostly everyone just quits mail if they goof and click an email link.
BUT some time ago at least one person invoked Mail and composed a message. This message, naturally, remained in the outbox ever since. That person learned that they can't send email that way, so ever since they just cmd-Q Mail.
BUT Before this person learned, they walked through the mail-config and told mail to try hitting smtp.mac.com:"nonExistantUser".
So that covers the lead-up. Two days ago, mail was invoked via a Safari link, BUT it wasn't quit, it was sent to the background.
Where it undoubtedly tried to send the outbox repeatedly until it was kicked off the network.
Here is what I don't understand:
Under this scenario of a mis-configured .mac address, will mail repeatedly try and fail to smtp at the maximum possible rate?
OR
Is the one other factor I am about to describe responsible?
The one other factor:
The clock battery is dead and there was a power failure at 4am that day.
The system clock reset to 1969.
Of course, nobody reset it.
Is mail.app one of the apps that the finder message warns "may behave erratically"?
(a GROSS simplification) does it have a bit of code like:
1 check time-of-last-send-mail-attempt
check newest-item-in-outbox
if newest-item more recent then last-send-attempt
do send-mail and record time-of-last-send-mail-attempt
and go to 1
else wait X minutes and go to 1
which, if the clock was mis-set to 1969 would always record a last-send-attempt prior to anything in the outbox and trigger a send loop.
Does anyone know if either Mail is tenacious about sending to a bad .mac address, or gets ridiculous under this circumstance for bad-clock-set?
Marc

Clock on display

Has anyone had problems gettitng the clock to display after IMG upgrade to 1.6?
Noticed today that all my boxes display the channel. When I tried to change to clock in the settings menu, it would not hold and continued the channel display.
Thanks
Solved!
Go to Solution.

He already said he went into the Settings Menu to fix it. I have seen other people post the same thing. It's a bug with the new 1.6 version. I don't know if the others were able to get it corrected or not.

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How do I use the PXI_clk10 backplane clock? It's not there!

Hi, folks!
This might seem a trivial question, but I'm completely at a loss here. I have made an RT-project in LV8 which (among other things) samples data continuously from two cards located in a PXI-system. All 32 (16+16) differential channels are used and one task for each card is configured in MAX. Since signal phase is an issue, I need to synchronize both tasks accurately. The lv8 code examples have a couple of VIs that should have been directly applicable to my situation, and I have studied them (and lots of others) in detail.
I have attached one example below that seemed to be spot on, and it makes use of the external PXI_Clk10 clock located in the pxi backplane. Here the confusion starts. When you attach a constant to the "source" input of the "sample clock" VI you get a drop-down list of possible sources. In the example code, PXI_Clk10 is chosen in this list, but when I try to do the same I discover that this option is simply not present. Only internal timing sources (located on the cards) can be chosen. If I configure the timing of the tasks directly in MAX, the PXI_Clk10 is an available option, but this leads to a vague error message when I start the tasks saying roughly that "it might be that you did not specify a name for the external sample clock...".
I have tried everything. My PXI-settings in MAX, routing signals via PFI-pins (didn't work at all), etc etc.
What is going on? Also: when routing a signal through a pfi-port, does this necessitate connecting the pfi-connectors physically or is the signal routed internally through the backplane? It doesn't help that I use BNC-2110 connector blocks. How can I be sure that the connectors on these blocks actually correspond to the terminals on the cards? I can't find a wiring diagram anywhere on the web.
Some facts: PXI-1031 chassis with PXI-8184 controller (dual boot) and two cards PXI-6229 / PXI-6259. These cards are located in slot 3-4.
Regards, Einar
Attachments:
Multi-Device Synch-Analog Input-Cont Acquisition.vi ‏77 KB

All PXI chassis produce PXI_CLK10 on the backplane (from an on-board 10 MHz oscillator), and most of them can also receive a 10 MHz clock from Slot 2 and broadcast that on the backplane. Some models can receive 10 MHz from a BNC connector on the back. Similarly, both 10 MHz and 100 MHz clocks are always available on PXI Express chassis.
Unfortunately, the 6143 and 6133 have no provision to connect to PXI_CLK10. This is likely because the master clock on those boards is 20 MHz, and there may not have been board space or room in the cost budget for a PLL to lock it to 10 MHz. Many other PXI products can use PXI_CLK10, such as the 6120. There is a list of products which use CLK10 and other PXI features here:
http://digital.ni.com/public.nsf/allkb/F4AD3B87DC8CD62E862571E3007042E5
I suspect this list is a little outdated; perhaps someone reading this knows where a more updated version is.
Hope this helps,
Ed

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