Best way to transfer data between loops in FPGA VIs

Question

Hi,
I'm using a FlexRio Board PXIe 7962, with an I/O module 5781.
I've set the Top level Clock to 80MHz (Base Clk 40M), and I'm implementing two loops in the FPGa VI: In the first one, I'm using a SCTL (20M) where I'm getting Digitized Data (1.5MHz) from the NI 5781, then multiplying it by a DDS Signal (1.8MHz), then I'm filtering (band-pass around 300kHz)) the product.
My question is: If what I've implemented is correct, what is the best way to transfer the first loop data running at 20MHz, to the second one running at 1MHz ? (without loosing Data of course since the signal interest is at 300kHz)
and similarly : what is the best way to transfer the second loop data running at 1MHz, to a Host VI ? DMA FIFOs?
Thank you in advance,
Zouhair
Attachments:
Diagram.png ‏158 KB

Answer 1

Zouhair wrote:
I've set the loop timer in the first frame to 4 clock ticks of 80MHz, so I imagine that what follows should not work under 20MHz, Am I mistaken?
Yes you are.  That SCTL will execute in the 20MHz clock time.  Everything else in the loop is just adding to that time.
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