Can't send Excel 2007 File via Send To Email Option after Acrobat Install

Normally, you can send an Excel 2007 file via email to someone by going to the Send option on the Excel file menu and choosing "Email." This will email an actual copy of the Excel 2007 file. However, since installing Adobe Acrobat 9 pro on my computer, this option, as well as the option to send to XPS are gone -- the only email option I have on that menu is to convert the file to a PDF and email it.
It seems to me that Acrobat should ADD options to menus but not remove any! Does anyone know how I can get those missing options (especially the one to email the actual file itself) back? I've tried Googling up a solution, but to no avail so far.
Thanks, in advance, for any help!
Laura

Thanks for taking the time to respond, Aditya!
I saw that MS support article when I was trying to solve this issue on my own, but the solutions it proposes won't work for me -- I can't set Outlook as my email client (this is a work computer and we use Lotus Notes) and I can't muck around in the registry (again, this is a work computer). I know I can attach the Excel via the attach command in the email client, but the main thing is I don't understand why Acrobat has removed that option from the Excel menu. Also, it removed the Send to XPS option (which I don't really care about, but it bothers me because it shouldn't be deleting anything)!
I even tried adding the Email command to the Quick Access Toolbar in Excel -- it let me add the button, but, when I click it, absolutely nothing happens.

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----------------------------------------------------------------------UART RX
-- File Downloaded from http://www.nandland.com
-- This file contains the UART Receiver. This receiver is able to
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use ieee.numeric_std.all;
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generic (
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i_clk : in std_logic;
i_rx_serial : in std_logic;
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o_rx_byte : out std_logic_vector(7 downto 0)
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begin
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r_RX_DV <= '1';
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r_RX_DV <= '0';
when others =>
r_SM_MAIN <= s_IDLE;
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TOP
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use IEEE.STD_LOGIC_1164.ALL;
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port(cl_k: in std_logic
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component random is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
Port ( clk :in STD_LOGIC;
output : out STD_LOGIC
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generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
port (
i_clk : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
end component;
--signal
signal mlebu:std_logic;
signal enabl:std_logic;
signal metu :std_logic_vector (7 downto 0);
begin
a:random port map( output=>mlebu,
clk=>cl_k
b:receive port map( i_clk=>cl_k,
i_rx_serial=>mlebu,
o_rx_dv=>enabl,
o_rx_byte=>metu
end Behavioral;
regards
halim

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