Can you please provide an example of test case using "Standard Data Output Cascade Mode"?

Hi,
I have tried creating a test to check  the "Standard Data Output Cascade Mode". In Vivado 15.1, Ultrascale,  it is working when I have data_width=1. However, if I modify the data_width to greater than 1, then I am not seeing the proper value for .CASCADE_ORDER_B.  Is this expected?
The RTL is top.v. The addr_width=16, data_width=4. The synthesized vm netlist, test_syn.vm. It contains  8 BRAMS but the .CASCADE_ORDER_B parameter setting in the vm netlist is:
.CASCADE_ORDER_B("FIRST"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("MIDDLE"),
.CASCADE_ORDER_B("LAST"),

Hi 
The parameter "CASCADE_ORDER_B" specifies the order of the cascaded block RAMs from the bottom to the top of the chain
for port B.
So the attribute value FIRST represents the bottom BRAM with respect to cascading. You can cross these attributes by opening synthesized design and observing the property of each BRAM.
Thanks,
Vinay

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