Cause for routing delay

Question

I have a motor control design on my spartan 6 lx9 device. As my design grew routing delays became large, which is normal
as i understand.
I was wondering what is the cause for the routing delay.  Is ist the actual time the signal needs in the fpga to
traverse the distance between the gates(traveling at some percentage of c)? If so, for a routing delay of 1ns this would mean
a routing lenght between gates of around 300 cm (assuming v=c) which seems like to much..

Answer 1

Short answer:  RC time constants due to FETs (likely).  I say "likely" because I cannot find, in a very short attempt, any Xilinx documentation on how their routing matrix works at the lowest level.
Routing matrix
This is an FPGA.  Unlike an ASIC, general purpose routing is configurable, and that configuration as far as routing is concerned is achieved with active elements controlled by SRAM bits, such as muxes, FETs.  It is not done with little nano-creatures spooling and unspooling wire within the FPGA based on your bitstream.  Consequently, to get from one side of a large FPGA to the other, using the general purpose routing, can take orders of magnitude longer than it would take light to traverse the same distance in free space.