Changing from "Pass Through" as Default in Blend Mode in a Group Folder Layer Set

Hello Forum gurus!
Using a MacBook Pro, 10.5.4. Painting with CS2. My question is two-fold.
When the Group layer folder in a layer set is selected, it is displaying the "Pass Through" blend mode by default. Is there a special convenience to this? (Best use for pass through blend mode)
Also, How may I change the default in this mode to be "Normal" as the setting when creating a Group folder layer set?
Thanks!!
Colene

Matthias, now I understand. We're both right from different perspectives. If you want the adjustment layer (should there be one within the group) to affect all layers below the group (perhaps because that's the way the image looked before you made the group in the first place), then Pass Through is your blend mode. If you want that adjustment layer to affect only those layers within the group (which I often do), then Normal (or some other) is your blend mode.

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Data has changed after passing through FIFO?

Dear experts,
I am currently working on a digital triangular shaping using the 7966R FPGA + 5734 AI. I am using LabView 2012 SP1.
Some days ago I have encountered a problem with my FIFOs that I have not been able to solve since. I'd be glad if somebody could point out a solution/ my error.
Short description:
I am writing U16 variables between ~32700-32800 to a U16 configured FIFO. The FIFO output does not coincide with the data I have been writing to the FIFO but is rather bit-shifted or something is added. This problem does not occure if I execute the VI on the dev. PC with simulated input.
What I have done so far:
I am reading all 4 channels of the 5734 inside a SCTL. The data is stored in 4 feedback nodes I am applying a triangular shaping to channel 0 and 1 by using 4 FIFOs that have been prefilled with a predefined number of zeros to serve as buffers. So it's something like (FB = Feedback node):
A I/O 1 --> FB --> FIFO 1 --> FB --> FIFO 2 --> FB --> Do something
A I/O 2 --> FB --> FIFO 3 --> FB --> FIFO 4 --> FB --> Do something
This code shows NO weird behaviour and works as expected.
The Problem:
To reduce the amount of FIFOs needed I then decided to interleave the data and to use only 2 FIFOs instead of 4. You can see the code in the attachment. As you can see I have not really changed anything to the code structure in general.
The input to the FIFO is a U16. All FIFOs are configured to store U16 data.
The data that I am writing to the FIFO can be seen in channel 0 of the output attachment.
The output after passing through the two FIFOs can be seen in channel 2 of the same picture.
The output after passing through the first FIFO (times 2) can be seen in channel 3 of the picture.
It looks like the output is bit-shifted and truncated as it enters Buffer 1. Yet the difference between the input and output is not exactly a factor of 2. I also considered the possibility that the FIFO adds both write operations (CH0 + CH1) but that also does not account for the value of the output.
The FIFOs are all operating normally, i.e. none throws a timeout. I also tried several different orders of reading/writing to the FIFOs and different ways of ensuring this order (i.e. case strucutres, flat and stacked sequence). The FIFOs are also large enough to store the amount of data buffered no matter if I write or read first.
Thank you very much,
Bjorn
Attachments:
FPGA-code.png ‏61 KB
FPGA-output.png ‏45 KB

During the last couple of days I tried the following:
1. Running the FPGA code on the development PC with simulated I/O. The behavior was normal, i.e. like I've intended the code to perform.
2. I tested the code on the development PC with the square and sine wave generation VI as 'simulated' I/O. The code performed normal.
3. I replaced the FIFOs with queues and ran my logic on the dev. PC. The logic performed totally normal.
4. Right now the code is compiling with constants as inputs like you suggested...
I am currently trying to get LabView 2013 on the development machine. It seems like my last real hope is that the issue is a bug in the XILINX 13.4 compiler tools and that the 14.4 tools will just make it disappear...
Nevertheless I am still open for suggestions. Some additional info about my FIFOs of concerne:
Buffer 1 and 2:
- Type: Target Scoped
- Elements Requested: 1023
- Implementation: Block Memory
- Control Logic: Target Optimal
- Data Type: U16
- Arbitrate for Read: Never Arbitrate
- No. Elements Per Read: 1
- Arbitrate for Write: Never Arbitrate
- No. Elements Per Write: 1
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Edited by: SKR on Feb 16, 2012 3:14 PM
Edited by: SKR on Feb 16, 2012 3:15 PM

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Jonathan.Knight wrote:
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