Creating large size shift registers in a SCTL

Hello, I am new to LabVIEW FPGA programming and I need to make a shift register with 1024 elements that is inside an SCTL. However, I ran out of FPGA resources when I try to compile it. Any Ideas on how can I implement it? Any help is greatly appreciated.

I don't think FPGA has enough area to use such big shift register. You'd better utilize FPGA memory to perform this task.

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Stat500 files are created with large size

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Hi Swathi,
Note 6833 will address your issue.
regards,
VInodh.

Better method than using a large number of shift registers?

I'm trying to work with example code provided free by stanford research systems (http://www.srsys.com/downloads/soft.htm).
Their example software alows the user to run an analog scan across 100 masses (the x axis) which progressively produces a graph of all the data. It repeats scanning (and updating the graph)until the user hits stop.
My goal is to find a way to make the program display the graph of the last scan while it is displaying the current scan (this way it is possible to compare the graphs and see how they change). But as best I can tell the data is generated and plotted in a while loop piece by piece so the best thing my labview inept mind has managed so far is using a large nu
mber of shift registers and graphing the points as they generated along with points that were generated 10 cycles ago in a different color.
So I hope to either find a good way to use shift registers to get values from over 100 cycles ago (which doesn't really seem to work unless i just make space for over 100 little arrows in my loop) or to find a better approach to the whole mess.
The example does not seem to use XY plot and to tell the truth I don't know exactly what its using to plot.
Can anyone offer any guidance or at least understand my question enough to point me in the right direction.
I'm including the stock example and my adaptation to it but if you need to use the included sub vi's the package is on that SRS webpage I listed above (look under RGA).
I suppose this may all be too much to ask but I can dream can't I?
Attachments:
original.vi ‏87 KB
changed.vi ‏92 KB

I certainly agree that the DAQ programming is the part leaving me most confused. I'll attach the package that I am trying to modify, the trouble is there are so many sub vis involved in actually acquiring the data that I am not entirely sure what format the data comes out in.
Perhaps to someone more skilled than I am with lab view the inner workings of this package would be clearer. If you are up for it then look at SRSRGAa simple analog.vi in SRSRGA61.lib and you can see what I'm working with.
I'll also attach my attempt to modify the code to make it work like altenbachs example... however somehow it would seem my timing/synchronization is off. Hope some of this makes sense, I'll see what luck I can have with get w
aveform components, I suppose I have been approaching this so far as if my DAQ was just giving me data points as opposed to a waveform.
Attachments:
rga_lv_61.zip ‏2132 KB
graph_app.1.vi ‏101 KB

Creating illustrations for large sizes, which software to use?

Hello everybody,
I'm an amateur, its my first discussion here,
My team from work will start a big project, we will build a space for visitors to an event. We will need several illustrations plots for the walls, the drawings has sizes like 6, 7 meters (width), with vectors and photos (jpeg, eps files). I have some experience with Ilustrator, but theres no way to create files larger than 577.95. Before I start, I want to hear your opinion about the best Adobe software to create these large size illustrations.

I second that. Setup your Illustrator File at 25%. Your Photoshop files will be 600ppi @ 25%; so their final ppi will be 150 @ 100%; suitable for large format digital printing. Raster/Document settings ( illustrator ) should be set for high res or custom where any raster effects will retain their appearance when scaled 400%. You might be able to prep your files @ 50%; if so, just adjust resolutions.

Calculate maximum value of subarray while creating it using a case structure and shift registers

I have two 1D arrays that contain cyclical information (kind of like a sine wave). One that contains information on position in degrees and another that contains torque. I would like to calculate the maximum torque value each time the position is within a certain range (e.g. from 30-80 degrees). The ranges are repeated - that's why it is cyclical. I use the "in range" function, a case structure and shift registers to build a new array with values that fall within the range I specify - this was the easy part (see VI attached). I'm struggling with a way to calculate a maximum value for each subarray formed when values are "in range". Your help is much appreciated.
Solved!
Go to Solution.
Attachments:
Simple Calculate between anatomical position range.vi ‏16 KB

It's not really noise - it's more inconsistency. So a position output can run: 20, 30, 40, 50, 60 etc. OR, it could run: 21, 24, 32, 41, 44, 51, 59 etc. But, it is always cyclical.
Attached you will find a .csv file with the data arrays - I'm using POS (ANAT) degrees column (column D if you open in excel). There you also see torque in ft-lbs along with some other information.
Attachments:
025C.csv ‏224 KB

Memory item as shift registers

Hello, I am new in LabVIEW Programming. Can I use memory item to make a large array of shift register inside a SCTL in LabVIEW FPGA? Large array of shift register consumes a lot of slices when i compile it. Can data be read and written(in different addresses) on a memory item in a single clock cycle? thank you

I am not sure I understand exactly what you are asking. If you are trying to use a Memory to implement a shift register you can certainly do that but I would recommend using a FIFO instead.
If you are trying to use an Array, Loop, and Shift Register to implement a memory that will work as well. Note that only LabVIEW FPGA 2012 and newer can infer block ram from this construct. In older versions the array will always be implemented in the standard FPGA logic using registers and utilizes more resources.
The above diagram will infer a block ram for larger array sizes.
Either way, the read and write addresses do not have to be the same in each clock cycle.

Replacing shift registers with queues or notifiers?

Hello World,
I'm using labView 7.1 with my first application, which is essentially a spectrum analyser and comparison to limits. now due to the parameters of the sampling 12000 samples/sec with 4096 point I have quite large chunks of data involved in rolling averages of 1 minute and rolling buffers that are an hour long. I'm pretty new to labview but I'm finding pretty easy to pick up except when it comes to optimisation and performance (I've been used to the microsoft approach until now) due to the fact that the instrument I'm building has to run in psuedo "real time".
I've been looking at replacing the shift registers with either queues or notifiers but I'm unsure if these techniques would result in improvements or not.
I'll attach a jpg of my main loop, I've only got the one but it is separated into three separate tasks but they are all governed by the data flow, DAQ then PROCESSING then REPORTING.
I've been told that by separating the loops and making them run in parallel LV will be able to compile it more efficeintly, but I'm unsure how to do that .
Cheers
Andrew
90% of all experts aggree that 1 out of 10 experts are wrong
Attachments:
Step 14 -Post Course Mk4d.jpg ‏376 KB

Fat Controller wrote:
Hello World,
I'm using labView 7.1 with my first application, which is essentially a spectrum analyser and comparison to limits. now due to the parameters of the sampling 12000 samples/sec with 4096 point I have quite large chunks of data involved in rolling averages of 1 minute and rolling buffers that are an hour long. I'm pretty new to labview but I'm finding pretty easy to pick up except when it comes to optimisation and performance (I've been used to the microsoft approach until now) due to the fact that the instrument I'm building has to run in psuedo "real time".
I've been looking at replacing the shift registers with either queues or notifiers but I'm unsure if these techniques would result in improvements or not.
I'll attach a jpg of my main loop, I've only got the one but it is separated into three separate tasks but they are all governed by the data flow, DAQ then PROCESSING then REPORTING.
I've been told that by separating the loops and making them run in parallel LV will be able to compile it more efficeintly, but I'm unsure how to do that .
Cheers
Andrew
Don't convert shift registers into queues or other things for performance reasons! LabVIEW has a lot of internal optimization logic when compiling your code which works best on shift registers. On a queue you will always copy the entire data of a message in or out even if you only need one byte of it.
Try to look at your architecture. You do want to do as much as possible in place. Try to completely avoid Append Array or Append String inside loops if possible. They are costly operations as they have to reallocate memory each time and often copy the entire data from the first array into the resized array. Better is to once preallocate an array of the necessary size, keep it in your shift register all the time and then use Replace Array Subset, Index Array and Array Subset nodes only on this. You will also have to maintian some index shich tells you up to where you have currently filled that array and that one is usualy best put into a shift register as well.
Rolf Kalbermatter
Rolf Kalbermatter
CIT Engineering Netherlands
a division of Test & Measurement Solutions

Is there and alternative to shift registers for saving data across iterations in a subVI operating inside a loop?

I am creating a subVI state machine (case structure) which will run inside a while loop which will be executing every 250ms. The reason I wanted to make the state machine case structure into a subVI is because I want to execute 64 of the machines within the same loop. The goal is to monitor certain types of voltage changes on 64 I/O channels on a FP2200 RT module and report periodic details about state changes to a database. My thinking was that by executing each independent machine in the same loop structure, I will only worry about one thread. It seems that the alternative of having one state machine thread per I/O channel is probably more than the RT module can handle. Please correct me if I am wrong on that.
The issue I'm now having is as I'm creating the state machine, I am finding that I need to keep track of some pieces of data from one loop iteration to the next. This is easy enough to do with shift registers but in order to use them, I have to create additional input nodes to my SubVI as well as output nodes. For example, I want to use a queue to buffer some I/O data but as of now, I have to create this queue outside the loop, pull it into the loop across a shift register, feed it to the subVI, and output it to the out Shift register. It would be better if I didn't have to output this queue because there's no reason for anything to have access to it outside the subVI. It just creates an extra set of wires to look at and makes me worry a bit about maintainability.
Is there a better way to approach this problem?

You could place a while loop inside your sub vi that has a true constant wired to the stop condition. Then add unitialized shift registers to that while loop to keep data between iterations.
or you could use a feedback node inside the sub vi

How do you open an image in a new window at a larger size?

Yes I am new at this.
Basically all I'd like to do is have a thumbnail on a page as a button, click it so it opens in a new window at a zoomed larger size.
I know this is probably simple but I can't figure out how to do this.
Anybody have a second to point me in the right direction?
I would appreciate it.

It sounds like you want to create a button hot spot. See this article:
https://blogs.adobe.com/indesigndocs/2010/12/hot-spot-button-workaround-for-indesign-dig-p ubs.html
You might also want to download the free DPS Tips app for an example of this and other DPS effects.

How to generate pseudo random noise(PRN) binary sequence using shift registers?

what is the block diagram to generate pseudo random noise (PRN) binary sequence of 1's and 0's using shift registers
please help
i need 2 submit this project in this week

This is a fairly simple homework problem. My hints (on the LabVIEW side):
1- look at while loops
2- look at shift registers on while loops with multiple input elements
3-look at the logic components, AND, OR XOR
Look at this wiki article: http://en.wikipedia.org/wiki/Linear_feedback_shift_register
Do the work, you won't learn if someone shows you how it is done! The palette that the previous post points to are of PRN and other "noise generators" but I suspect that is not what you are after.
Know that creating a PRN with a reasonable number of shift register taps produces very pseudo results, as the "random" pattern begins to repeat pretty quickly, thereby making it not a truly random number.
When you have an attempt that is sort of working and want additional suggestions, post the code here. We won't do your work, we will help you try to do it, and learn it, yourself.
Putnam
Certified LabVIEW Developer
Senior Test Engineer
Currently using LV 6.1-LabVIEW 2012, RT8.5
LabVIEW Champion

Creating large pdf document

Help, I have created a magazine for a local club which is in excess of 100mb and it won't upload to a PDF document, can you please help?

Hi wendyclewley,
There is a 100 MB file size limitation for submitting files to the Create PDF service.
But with Acrobat you can create large files.
You can use free trial service of 30 days.
If it meets your expectation then you can purchase the full version.
Regards,
Florence

Static Shift registers

My understanding of shift registers is that if you don't initiaze them
then they will hold the value from the last instance, hence be static.
I've created a subvi and placed multiple copies in a case statement,
all it does is check to see if the value has changed, yet when it runs
the second time it starts out at zero when it should be whatever
number went through the sub the last time.
Am I missing something here?
Bundle to byte array contains single to byte array sub vi
Ron
Attachments:
Bundle to Byte array w change.vi ‏29 KB
Single to Byte array w change.vi ‏10 KB

You should always consider initializing shift registers. Keep in mind that if you just opened a VI that contains uninitialized shift registers, it won't remember the data from the last time it was run (because it has been unloaded from memory since then), so it's more likely the values in that shift register are garbage. That could be even more dangerous, since how LabVIEW interprets that data could cause very strange and erratic behavior in your application.
Here's my solution that works for Functional Globals and general shift registers: Consider initializing them the first time the VI is called inside the While Loop, as demonstrated below:
The First Call VI outputs a true the first time that instance of it is called, and false every other time. For Functional Globals you could alternatively have a dedicated Initialize case to perform this function. The advantage of the technique listed above is that you are guaranteed initialization on the first call, regardless of whether the client programmer remembers to call an initialization case.
Message Edited by Jarrod S. on 04-11-200612:33 PM
Message Edited by Jarrod S. on 04-11-2006 12:33 PM
Jarrod S.
National Instruments
Attachments:
Pic1.jpg ‏7 KB
Pic2.jpg ‏14 KB

HiDPI (2x) don't export correct size. Even when I imported the image in larger size (original)

It is an image of 5118X1441, and 144 resolution.
From the assets panel I imported like a larger size image
When I see her on preview in browser, size automatically switches to a smaller one again. The same happens when I export or upload to server.
Another problem is that the images are not vicibles on iPhone 5s (have retina display) Not even the 72 pixels version.
I would appreciate any help.

Hi,
Check this article, under "Exporting HiDPI images"
Adobe Muse Help | Creating High Resolution websites
See if that helps. Do let me know if you have any question.

Need help with while loop and shift registers

I have a large data set and need to read in the data at maybe 200 samples at a time, process these samples through my VI, and have it append and concatenate a separate lvm file. The part where I am confused is the shift registers. How do I limit the number of samples read in an iteration? How do I get the while loop to stop when all the data are read in?
I've attached my diagram, maybe there is something wrong with my technique?
Solved!
Go to Solution.
Attachments:
shiftreg.JPG ‏56 KB

This will give you an idea. There are plenty of other (probably more efficient) methods. This is a basic, quick and dirty solution to help you grasp the overall concept.
Using LabVIEW: 7.1.1, 8.5.1 & 2013
Attachments:
ShiftRegLoop.JPG ‏54 KB

For adding about 70 shift registers to my VI , will it affect the performance of the project or it depends on my PC ??

I have 70 shift registers to accumulate date from 70 channels to plot it every channel individually , will these shift registers affect the performance of the project or it depends on my PC ??

Osama90 wrote:
I have 70 shift registers to accumulate date from 70 channels to plot it every channel individually , will these shift registers affect the performance of the project or it depends on my PC ??
It will certainly affect your performance and ability to handle/change your code. Change it to an array of plots, either as a 2D array (if using the same sampling rate), or an array of clusters with the channels (1D array?) as data. From a machine perspective 70 SRs should work, but not from a person perspective.
/Y
LabVIEW 8.2 - 2014
"Only dead fish swim downstream" - "My life for Kudos!" - "Dumb people repeat old mistakes - smart ones create new ones."
G# - Free award winning reference based OOP for LV

Creating large size shift registers in a SCTL

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