DAQmx Sample Clock (on-board clock) effects

Why would I get slightly different readings when using the Sample Clock (onboard clock) and not using it? On several different cards, I've noticed slightly lower levels of analog input when using the Sample Clock and not using it.
thanks
Richard

Thanks Doug. In LabVIEW, on a SCXI-1102 and a 1502. (DAQ is a PCI-6221).
I understand the benefit of the DAQmx buffer that gets setup when you use Sample Cock, but if I'm just taking "1Chan 1Samp" samples, I wouldn't expect a difference. The sample taken with the Sample Cock included in the Task is a few tenths of a volt less than a the reading taken from a Task not including the Sample Clock (on a ~1V signal).
Message Edited by Broken Arrow on 01-14-2009 04:21 PM
Richard

Similar Messages

Daqmx Sample clock

Hello,
I am using Daqmx Sample clock function and I am a little confused about the input " rate" of this function.
In Labview Help, this inut is defined as below:
"rate" specifies the sampling rate in samples per channel per second.
Now I set this " rate" to be 8000 and I have 8 channels, Does this mean that the sampling rate of the whole device is 64000? The samples per channel is 1000, what is the buffer size allocated by labview? Is it 8000?
Thanks in advance, I am looking forward to the replies.

Below is another knowledge base article.
http://digital.ni.com/public.nsf/3efedde4322fef19862567740067f3cc/dbe7ac32661bcf9b86256ac000682154?OpenDocument
You said that you have eight channels. Are these channels setup in MAX and if so are they global channels or just one Task? Or are you creating a Task in LabVIEW?
If you are reading these channels as a single Task, then each channel is being sampled at "sample rate". Then the buffer size is dependent on "sample mode". If it is continuous then use the chart, but if "Sample Mode" is finite then, NI-DAQmx allocates a buffer equal in size to the value of samples per channel.
When doing finite, "sample rate" is the rate at which the channel will be sampled and "samples per channel" is the number of samples to return. So if sample rate = 1000 and number of samples to return = 100, then 100mSeconds of data will be returned ("number of samples to return/"sample rate"). In other words the channel will be sampled at 1000 until a total of 100 samples has been received.
Chad

Must startup clock equal configuration clock?

Hi,
I have a Virtex-6 configured from platform flash in selectMap slave (external clock), configuration clock provided to both by an on-board clock generator (40Mhz, must be fast for PCIE <100ms config time).
Often, the FPGA done bit goes high (external LED...) , everything is OK (read status register via IMPACT) except :
[5] GTS_CFG_B STATUS : 0
Signal integrity on CCLK is OK (checked with scope).
Bit file generated using default options.
A local AFE suggested setting the StartupClk option to UserClk.
Question: must the start-up clock be the same as the configuration clock? why?
could this explain the intermittent failures I'm seeing?
thanks in advance, Gal.

Since you are doing the configuration in slave mode, the CCLK will not be generated by the config logic.

Is it possible to have Clock in and clock out times in weekly view

Hi,
We have Daily View and Weekly View in Record Working Time iview in ESS.We can set the Clock in and Clock out times in Daily view if we check the With Clock Times checkbox in Data Entry Profile.But we want to have same Clock in and Clock out in Weekly view without any developement.
If it not possible thru config how much will be the Development Effort
Thanks
Bala Duvvuri

Siddharth,
can you please elaborate this
Thanks
Bala Duvvuri

Is it possible to have clock in and clock out in weekly view

Hi,
We have Daily View and Weekly View in Record Working Time iview in ESS.We can set the Clock in and Clock out times in Daily view if we check the With Clock Times checkbox in Data Entry Profile.But we want to have same Clock in and Clock out in Weekly view without any developement.
If it not possible thru config how much will be the Development Effort
Thanks
Bala Duvvuri

Hi Bala
You can have clock in and clock out in a weekly view.
you have to change the data entry profile settings.
In general settings tab in data entry profile click the with clock times button and maintain the Period type to 02 in time settings tab.
And you can view the weekly entry in clock in and clock out.
Ravee
+91.99206.33669

Clock in and clock out issue

Hi All,
I am looking for a solution for the below issue. Please help me out
Clock in and clock out details from third party terminal are stored in SAP in IT2011.
My requirement is if the duration between first clock in and last clock out is less than 4 hours system should consider as LOP for that day.
can you please let me know if I should a PCR or any other way.
Regards
Vish

You can do as below:
Normally time type 0000 is used for normal attendance hrs in time schema PCR's like TP09, TP10, TP11.
Before CUMBT function, call a PCR using ACTIO to do as below:
If the daily value is time type 0000 < 4.00, insert a w/t for LOP absence hrs for the day. The hrs can be as per the business rules:
a)from IT 7 - provided IT 7 has the correct data from WSR and WSR is correct.
HRS=IDAHRS           daily hrs
or
HRS=IWEHRS HRS/5    weekly hrs/5
or
b)from the DWS for that day
HRS=S        -DWS hrs including any substitution
See example below assuming 0000 time type for normal attendance hrs, 8001 time w/t for LOP hrs.
             D   HRS=D0000    HRS?4
<                HRS=IDAHRS ADDZL8001
In payroll,
- Time w/t's from time eval are imported by ZLIT function (usually in XT00 sub schema).
- PCR XPPF and its sub PCRs this w/t hrs can be used to reduce the partial pay factors e.g. /801 used to reduce the payments like basic pay, etc.
- PCR XVAL uses these factor w/t's to reduce the payments.

Need support - Writing PCR (To find missing clock-in and clock-out)

Hi Gurus,
I need support on writing PCR on below scenario.
Scenario:
Need to determin missing clock-in and clock-out punches and generates LOP for the same.
Regards,
Raji

Hi,
In this case you need to build logic like the follow.
Assumptions: mulitiple time pairs are there.
First check employee present or not, then check data coming through time events or not then check first pair after that take HRS value as start time of first pair if yes store day balances in ABCD. in case of No check Last pair take end time store in as day balance BCDE. after that based on day balance values genearte wagetypes in another PCR.
Note: in same PCR you can store wage type aslo.

Time Report required to capture clock in and clock out.

Hi All,
We have requirement where in we need to present the following details in the report to the client:
1) Clock in
2) Clock out
3) PLanned working hours
Pls let me know if there is any standard report for the same or any sap query that can be copied and used.
We are using negative time management with the Time management status as 7.
Points would be awarded.
Thanks,
Deepali

Hi Deepali,
RPTCORDBVIEW (Display Clock-In/Out Corrections (Database)): You can use this report to view all information about the clock-in/out corrections that have been entered.
Could you please follow the link bellow for more the details:-
http://help.sap.com/erp2005_ehp_03/helpdata/EN/79/e71940a65ec442e10000000a1550b0/frameset.htm
Hope this info was helpful to you..
Regards,
Sagar.

My key says "Error - key importing failed gpg: key 5D391D97 was created 55491 seconds in the future (time warp or clock problem)" The clock in the computer is f

When I create a key and send it to the person I want to begin communicating with encryption, the other person gets this when importing the key: "Error - key importing failed
gpg: key 5D391D97 was created 55491 seconds in the future (time warp or clock problem)"
The clock is set properly. Can you assist me in solving this error? This happens in a PC computer running WIndows 7.
Thank you
Cecilia

I created a different key and I have the same problem. I can send you the public key in case that helps solve the problem but you need to provide me with an email address because I cannot upload it here.
Thank you for your assistance.
Cecilia

Type of on board clock for T5120 ?

Hi,
Does anyone know what type of on board system clock for T5120?
Thanks!

Hello Ganga,
There is the DAQmxSetAOUseOnlyOnBrdMem is a NI-DAQmx C Property which
is discussed in the NI-DAQmx C Reference Help, which is installed with
the NI-DAQmx driver under Program Files >> National Instruments
>> NI-DAQ. This function specifies whether to write samples
directly to the inboard memory of the device, including data FIFOs,
bypassing the memory buffer. You will need to set this property
and write your data before starting the task. The default
behavior is to regenerate the data written to the buffer, the different
regeneration modes are discussed in this KnowledgeBase, if you want to change the default behavior the NI-DAQmx C Reference Help is a great resource.
Regards,
Micaela N
National Instruments

Can I acquire waveform at faster sampling rate using external clock?

I am trying to acquire waveform at a sampling rate of 1MHz. My 6036E card is maxed out at 200KHz. Is there a way to achieve a sampling rate of 1MHz using an external sample clock? Your PFI pin can take external clock as an AI sample clock, right?

Hi,
I remember I asked the similar question before in the NI forum, they reply me:
the max sample rate (scan/s/channel) cannot be greater than your board max sample rate, even you use external scan clcok. So the answer is no for your case.

E-series board clock synchronization (master/slave)

Platform: Win2k, LabView 6.02i, NI-DAQ 6.9.2
I have two PCI 6071E DAQ boards and would like to define one of them as a master that uses its internal samping clock and the second - as a slave, getting its sampling clock from the first one. I used the example "Two E Series Shared Scan Clock " example to do it, but got strange results.
The question is, how can I check that the slave really uses master's scan clock (say, using a two-beam oscilloscope) ? Are there outputs on 6071E that can prove that the boards are synchronized ?
Thank you,
Sergey.

Hello;
Since the slave board on that Labview example VI is configured to expect an external Scan clock pulse train, and later on the same example the Scan clock is defined to be one of the RTSI lines, if the slave board is acquiring any data, that means that the synchronization is in place.
To double check the synchronization visually, you can hook up a 2 channel scope, and maybe hook up two waveforms you know are in phase, one to channel 0 of the master boar and the other to channel 0 of the slave board. Then, configure the scope to trigger of channel 0, and connect channel 0 of the scope to the master board and channel 1 of the scope to the slave board.
With that setup, you will see both waveforms in phase on the scope.
Hope thie helps.
Filipe A.
Applications Engineer
National Instruments

Sample with an external clock with a SCXI 1140 (8 channel sample/hold amplifier)

I have a SCXI 1140 (8 channel sample/hold amplifier) and a SCXI 1305 card (BNC).
I want to sample an analog signal with external frequency (SMB connector).
I plug an analog signal on the channel 0 and a TTL signal on SMB connector "hold/clock" (the jumper corresponding to the SMB connector is on Hold postion).
I use the "ACQUIRE N SCANS - EXT SCANSCLK.VI" LabView example with :
DEVICE=1
CHANNELS [0]=SC1!MD1!0
CLOCK SOURCE=I/O CONNECTOR
CLOCK SOURCE STRING=SC1!MD1!
When I execute the example, I have the error -10 001 (problem with clock source string).
If I used CLOCK SOURCE=INTERNAL there is no error, but I do not sample with hold signal !
What is the probl
em with the string ?
Is there another solution for sampling whith an external signal ?

The error that you're seeing is being generated because the clock source string should be "sc1!md1" not "sc1!md1!". It's the "!" at the end of the string that is causing the error.
Regards,
Erin

Menu Clock Hangs, System Clock remains working

Since upgrading to Mountain Lion, the menu clock hangs randomly. When I cursor over that area of the system menu bar the spinning beach ball appears. In System Preferences the clock reads the correct time, but none of the other options can be selected. An older OS post recommended quitting SystemUIServer using the Activity Monitor utility. That clears the problem, but it recurs. In that older post it suggests removing a preference file and having it regenerated, but the file specified doesn't seem to exist in Mountain Lion.
Thoughts?

None of these radical fixes is acceptable (or, for that matter effective).
Here's my symptoms, fwiw:
The clock in the menu bar regularly hangs. Hovering the mouse pointer over it shows the swirling pinwheel busy icon. The system knows what time it it - for instance, if I create a file it shows the right creation time.
When I access System Preferences - Date/Time, Show date and time in menu bar is not checked (though it is showing). When I check it, it unchecks itself after a while. Meanwhile, it shows the swirling rainbow pinwheel.
This animal is sick - and from the long history in this thread, has been for a long time.
Why does Apple not fix this?

Hardware clock and system clock don't match

hello. i recently upgraded to kde 4.7, and i don't know if it's the culprit or not, but my system clock is now ahead of the hardware clock by the timezone offset.
my timezone is Asia/Manila, which is UTC+8. so if the correct time is 00:00, the system time is 08:00.
i dual boot with windows so the HARDWARECLOCK setting in /etc/rc.conf is set to localtime.
interestingly, the commands "hwclock --show" and "date" both show PHT as the timezone, but with the aforementioned time skew. to illustrate:
# hwclock --show
Fri 05 Aug 2011 10:45:02 AM PHT -0.500309 seconds
# date
Fri Aug 5 18:45:02 PHT 2011
running "hwclock --hctosys" fixes the problem while logged in, but restarting the computer reverts the problem. i could put a daemon that runs the command at startup, but i never needed to do that before and i'm not inclined to at the moment. i think this is just a misconfiguration somewhere.
thanks for any help you could give.

hello. it is
hwclock from util-linux 2.19.1
Using /dev interface to clock.
Last drift adjustment done at 1312511647 seconds after 1969
Last calibration done at 1304274137 seconds after 1969
Hardware clock is on local time
Assuming hardware clock is kept in local time.
Waiting for clock tick...
...got clock tick
Time read from Hardware Clock: 2011/08/05 12:08:46
Hw clock time : 2011/08/05 12:08:46 = 1312517326 seconds since 1969
Fri 05 Aug 2011 12:08:46 PM PHT -0.690104 seconds

DAQmx Sample Clock (on-board clock) effects

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