Data Reconciliation between BI and R/3 systems

Hi Gurus,
I want to know how to reconciliation the data between BI and R/3 systems.
is there any easy mentods to reconcile the data.i have also gone through the HOW TO GUIDE document, that document dosen't help me out.
Regards
Sreenivas.Y

1) Either we can reconcile using standard R3 tables eg VBAK , VBAP for sales .
2) You can go for automatic reconcillation where you will have to create a reconcillation data source and extract it to BW using virtual cube (Virtual cube would extract real time data from R3).
Include original cube and this virtual cube in a multiprovider .
Make a report taking keyfigures from both the infoproviders and add a column for difference .If there is 0 difference it means BW data matches with R3 .

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Tony
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I have observed that SNP Planned order availability date is not matching between APO and ECC. Details are as follows.
I ran SNP Optimizer with bucket offset of 0.5. After publishing the optimizer created planned orders to ECC, only start date is matching.
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I am using PDS as a source of supply.
Fixed production activity in SNP PDS is 1 day.
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Hi Venkadesh,
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end date of the last activity of the order, the receipt date
always identifies this as inconsistent. You cannot rectify
inconsistencies of this type by using CCR."
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Most efficient data transfer between RT and FPGA

This post is related to THIS post about DMA overhead.
I am currently investigating themost efficient way to transfer a set of variables to a FPGA target for out application. We have been using DMA FIFOs for communications in both directions (to and from FPGA) but I'm recently questioning whether this is the most efficient approach.
Our application must communicate several parameters (around 120 different variables in total) to the FPGA. Approximately 16 of these are critical meaning that they must be sent every iteration of our RT control loop. The others are also important but can be sent at a slightly slower rate without jeopardising the integrity of our system. Until now we have sent these 16 critical parameters plus ONE non-critical parameter over a DMA to the FPGA card. Each 32-bit value sent incorporates an ID which allows the FPGA to demultiplex to the appropriate global variables on the FPGA. Thus over time (we run a 20kHz control loop on the RT system - we have a complete set of paramaters sent @ approx. 200Hz). The DMA transfers are currently a relatively large factor in limiting the execution speed of our RT loop. Of the 50us available per time-slot running at 20kHz approximately 12-20us of these are the DMA transfers to and from the FPGA target. Our FPGA loop is running at 8MHz.
According to NI the most efficient way to transfer data to a FPGA target is via DMA. While this may in general be true, I have found that for SMALL amounts of data, DMA is not terribly efficient in terms of speed. Below is a screenshot of a benchmark program I have been using to test the efficiency of different types of transfer to the FPGA. In the test I create a 32MB data set (Except for the FXP values which are only present for comparison - they have no pertinence to this issue at the moment) which is sent to the FPGA over DMA in differing sized blocks (with the number of DMA writes times the array size being constant). We thus move from a single really large DMA transfer to a multitude of extremely small transfers and monitor the time taken for each mode and data type. The FPGA sends a response to the DMA transfers so that we can be sure that when reading the response DMA that ALL of the data has actually arrived on the FPGA target and is not simply buffered by the system.
We see that the minimum round-time for the DMA Write and subsequent DMA read for confirmation is approximately 30us. When sending less than 800 Bytes, this time is essentially constant per packet. Only when we start sending more than 800 Bytes at a time do we see an increase in the time taken per packet. A packet of 1 Byte and a packet of 800 Bytes take approxiamtely the SAME time to transfer. Our application is sending 64 Bytes of critical information to the FPGA target each time meaning that we are clearly in the "less efficient" region of DMA transfers.
If we compare the times taken when communication over FP controls we see that irrespective of how many controls we write at a time, the overall throughput is constant with a timing of 2.7us for 80 Bytes. For a small dedicated set of parameters, the usage of front panel controls seems to be significantly faster than sending per DMA. Once we need to send more than 800 Bytes, the DMA starts to become rapidly more efficient.
Say hello to my little friend.
RFC 2323 FHE-Compliant

So to continue:
For small data sets the usage of FP controls may be faster than DMAs. OK. But we're always told that each and every FP control takes up resources, so how much more expensive is the varsion with FP controls over the DMA.
According to the resource usage guide for the card I'm using (HERE) the following is true:
DMA (1023 Elements, I32, no Arbitration) : 604 Flip-Flops 733 LUT 1 Block RAM
1x I32 FP Control: 52 Flip-Flops 32 LUTs 0 Block RAM
So the comparison would seem to yield the following result (for 16 elements).
DMA : 604 FLip-Flops 733 LUT 1 Block RAM
FP : 832 FLip-Flops 512 LUT 0 Block RAM
We require more FLip-Flops, less LUTs and no Block RAM. It's a swings and roundabouts scenario. Depending on which resources are actually limited on the target, one version or the other may be preferred.
However, upon thinking further I realised something else. When we use the DMA, it is purely a communications channel. Upon arrival, we unpack the values and store them into global variables in order to make the values available within the FPGA program. We also multiplex other values in the DMA so we can't simply arrange the code to be fed directly from the DMA which would negate the need for the globals at all. The FP controls, however, ARE already persistent data storage values and assuming we pass the values along a wire into subVIs, we don't need additional globals in this scenario. So the burning question is "How expensive are globals?". The PDF linked to above does not explicitly mention the difference in cost between FP controls and globals so I'll have to assume they're similar. This of course massively changes the conclusion arrived to earlier.
The comparison now becomes:
DMA + Globals : 1436 Flip-Flops 1245 LUTs 1 Block RAM
FP : 832 FLip-Flops 512 LUT 0 Block RAM
This seems very surprising to me. I'm suspiscious of my own conclusion here. Can someone with more knowledge of the resource requirements differences between Globals and FP controls weigh in? If this is really the case, we need to re-think our approach to communications between RT and FPGA to most likely employ a hybrid approach.
Shane.
Say hello to my little friend.
RFC 2323 FHE-Compliant

PPDS production order dates mismatch between APO and R3

Hi Friends,
We are facing one problem regarding production order date mish match between R3 and APO systems specific to a product.
The product is planned in PPDS and the order automatically transfer to R3 through online CIF.
PPM has got two operations 0010 and 0020 and activity relationships are like this:
P(0010) - P(0020) Start - Start relation ship
S(0010) - P(0010) End - Start relationship.
In PPDS dates are shown as :
on operation 0010 the start/end dates are shown as 08.15.09 to 08.22.09
on operation 0020 the start/end dates are shown as 08.15.09 to 08.22.09
Overall order start date is 08.15.09
Overall order finish date is 08.22.09
and in R3 dates are shown as:
on operation 0010 the start/end date are shown as 08.15.09 to 08.22.09
on operation 0020 the start/end dates are shown as 08.22.09 to 08.29.09
Overall order start date is 08.15.09
Overall order finish date is 08.29.09
The order is off one week (APO vs R3) with start and finish dates.
if we change DS Board settings to ignore internal relationships manually then the dates are matching exactly in APO and R3.
We want the production order dates to be matched without manual intervention.
Could some one please provide some hints on what is happening here and how to correct it.
Thanks.
Krish

Hi Friends,
Thanks a lot for your valuable replies in this regard.
Actually this problem is in production environment and it took some time to test the problem with the master data modifications
you suggested.
As DB and Siddhrath mentioned, the problem was with routing definition. There is no parallel sequence maintained in the routing but there is start-start relation maintained in APO PPM.
We corrected the routing definition and checked the order dates. Now the dates are matching in R3 and APO.
I am awarding DB and Siddharth each five points in this regard.
Once again thank you all for your time and valuable replies.
-Regards
Krish.

Data Reconciliation between BI and R/3 systems

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