Dataflow in HLS doesn't work in real hardware implementations (13 benchmarks)

Question

Hi all,
I use Vivaod HLS to generate a hardware IP core using streaming interface (hls::stream) and implement it using Vivado. (ARM controls DMA to send the streaming data to hardware IP and after the hardware processing the data, use DMA to transfer the result back to memory from hardware).
The C code in HLS is applied with Dataflow pragma, and the initialtion interval (II) is less than the latency reported by HLS (This is correct, because we are utilized the task level parallelism). Theoretically, the execution time should be like the following graph (Providing 4 frames data and invoking this hardware IP for 4 times) , which means that the execution cycle should be 16386*2 + 95811 * 4
However, in reality, when I implement it on real hardware and measure the execution cycle via SCUtimer on ARM, the execution time is (16386*2+ 95811) * 4, which means that we do not have any benefit from this "dataflow" task level parallelism. The whole hardware is correct and all the results sending back from device to memory are verified. The way I invoke this hardware in the host code is similar to the following pattern:
for (i=0; i<4; i++) {
start timer st;
1. Send i-th frame data from DMA to device;
2. Send i-th frame result from device to DMA;
end timer et;
time += et-st;
Any steps or things I miss here? Does anyone make the dataflow work on the real implementation? Or it just works on the HLS and can not support in Vivado.
Thanks,
Henry

Answer 1

henry.c wrote:
for (i=0; i<4; i++) {
start timer st;
1. Send i-th frame data from DMA to device;
2. Send i-th frame result from device to DMA;
end timer et;
time += et-st;
Hello Henry,
The way you test this does not reflect your flow / dataflow diagram.
In your test, the VHLS IP runs between steps 1 and 2 but you are still serially executing everything : DMA in , buffer in , compute , buffer out, DMA out, DMA in, buffer in, compute, buffer out, DMA out , DMA in, buffer in etc so the total time is the sum of the individual execution.
In your flow diagram (which is the same as the UG description for dataflow) you have the input buffering for frame N happening before the end (and even before the start) of output buffering of frame N-1; so you need to have your embedded code processor doing exactly that.
I'm not so familiar with the way the DMA works and if you can stack up transactions beforehand; that would be the easiest, otherwise you'll have to make it work some other way.
Also your timing measurements should be outside the for loop so that you measure the total execution. (<- that sentence is the EDIT)
I hope this helps.