Debug Probes @ Vivado

Question

Hello everybody!
I tried to include some debug probes in Vivado 2015.2 after synthesis according to the working flow with PlanAhead/FPGA editor.
I found the AR#53266 with attached tcl script.
First I searched for nets:
get_nets *LED*
LED[0] LED[1] LED[2] LED[3] LED[4] LED[5] LED[6] LED[7]
Then I entered
apps::addProbe <>/<>/LED[0] F3 LVCMOS33 Debug0
Vivado answered with:
WARNING: [Vivado 12-507] No nets matched '<>/<>/LED[0]'.
WARNING: [Vivado 12-180] No cells matched 'get_cells -filter IS_PRIMITIVE -of [get_nets -segments {<>/<>/LED[0]}]'.
WARNING: [Coretcl 2-30] Cannot find net '<>/<>/LED[0]'.
I'm a little confused, because I really don't get it?!
Thanks in advance!
Lei

Answer 1

 Install the tcl app in 2015.2 by running following tcl command
tclapp::install debugutils
xilinx::debugutils::add_probe -help
This will give you the details about the proc and how to use it.
Example given is
::xilinx::debugutils::add_probe -net cpuEngine/or1200_cpu/p_0_in[10] -port myprobe -iostandard HSTL -loc W26