Debugging: Using JTAG to axi Master: Can't write to the memory

Hello,
I am trying to make a very simple design in order to write and read to the memory using JTAG to axi master IP core. I did my design based on the following quick take video:
https://www.youtube.com/watch?v=btJ5Q7psf9M
After downloading the bitstream and trying to work with the tcl, everything goes well until when I want to use the write command:
run_hw_axi [get_hw_axi_txns $wt]
I will receive the following error :
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION FAILED
INFO: [Labtoolstcl 44-481] WRITE DATA is: 44444444_33333333_22222222_11111111
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
What is wrong?
Here is more detail about my design:
1. The only top module is the vhdl wrapper for the block design which has been generated by the ip integerator
2. The clock is running at 100MHz.
3. the reset is grounded to 0, i.e. I don't have external reset signal
4. I have tried different clock frequency while connecting it to the JTAG, didn't help
Thanks,
Aryan

I removed the clocking wizard ip and connected the clock directly to the design block. works perfectly now

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JTAG to axi Master: Can't write to the memory

Hello,
I am trying to make a very simple design in order to write and read to the memory using JTAG to axi master IP core. I did my design based on the following quick take video:
https://www.youtube.com/watch?v=btJ5Q7psf9M
After downloading the bitstream and trying to work with the tcl, everything goes well until when I want to use the write command:
run_hw_axi [get_hw_axi_txns $wt]
I will receive the following error :
ERROR: [Xicom 50-38] xicom: AXI TRANSACTION FAILED
INFO: [Labtoolstcl 44-481] WRITE DATA is: 44444444_33333333_22222222_11111111
ERROR: [Common 17-39] 'run_hw_axi' failed due to earlier errors.
What is wrong?
Here is more detail about my design:
1. The only top module is the vhdl wrapper for the block design which has been generated by the ip integerator
2. The clock is running at 100MHz.
3. the reset is grounded to 0, i.e. I don't have external reset signal
4. I have tried different clock frequency while connecting it to the JTAG, didn't help
Thanks,
Aryan

I removed the clocking wizard ip and connected the clock directly to the design block. works perfectly now

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Debugging: Using JTAG to axi Master: Can't write to the memory

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