Derived clock problem?

Question

I am tring to derive a 25MHz clock using a NI PXI-7842R and labview project won't allow that exact clock
But when I try doing the same thing for a PXI-7830R target, I am sucessful.
What is going on?
I am choosing a base clock of 40MHz
to get 25MHz, the multiplier is 5 and the divisor is 8
When I right click on New Derived clock, I only get the option of entering a new clock frequency.
Why does the tool not let me just specify the multiplier and divisor?
I am using Labview version 2010
Solved!
Go to Solution.
Attachments:
derived clocks.lvproj ‏16 KB

Answer 1

LabVIEW FPGA does use the built-in DCMs for the Virtex 5,
however, the parameters for the DCM with a 40 MHz input clock do not allow for
25 MHz on the Virtex 5.
In trying to instantiate a derived clock, there are four
possible options, a 1X clock, a 2X clock, CLKDV, which is a phase-aligned clock
operating at a fraction of the input clock, and CLKFX, which takes the
multiplier and divisor and creates a clock of (M/D) * clock in rate.
Obviously, 1X and 2X will not work because they yield a 40 MHz and 80 MHz clock, respectively.  The other two are limited by the specs for
the DCM.
In looking at the Virtex-5 FPGA User Guide in the section
Clock Management Technology, you will see a section for DCM Attributes.  CLKDV_DIVIDE (p. 58) is an attribute set for the DCM
that tells the DCM what rate the CLKDV output should run at.  If you look at the available attributes, you
can see that 5/8 does not fit into one of the valid configurations, so we can’t
use CLKDV.
We also cannot use CLKFX because the Virtex-5 DC and
Switching Characteristics Data Sheet shows that the valid ranges of CLKFX are
32 MHz to 140 MHz for the Low-Frequency Mode and 140 MHz to 350 MHz for the
High-Frequency Range (p. 57).  Since 25 MHz is below the minimum rate, we can't create it from this DCM output port.
You can do this on the PXI-7830R because that
has a Virtex-II FPGA with different characteristics and attributes.
Donovan