Dual Processors -- How Exactly Does Logic Use Them?

I've searched this forum but haven't found any definitive, exacting information that would answer this question: How does Logic utilize both processors of a Dual Processor G5?
Real information -- not guesses -- would be really appreciated. Thanks.

Rohan, thanks for your detailed reply.
Actually, I hadn't surmised anything about how the dual processor architecture was implemented, except for the one idea that, perhaps, the second processor would be used to accellerate screen graphic drawing while the first one ("primary processor"??) dealt with audio matters. But I have the feeling this ain't happenin'.
I haven't yet put Logic through any serious paces yet with my new G5/Logic system, so I've yet to see the System Performance meter read on anything but the left side of the Audio Meter.
But back to the graphics drawing situation, compared to my G4 dual 450 (with dual head Radeon graphics accellerator card) running an older version of Logic, the response of Logic 7 running on my new "whoop-tee-doo" G5 dual 2.7 is deathly slow in certain respects...
For example, I recorded 8 simultaneous audio tracks. When I hit stop, the spinning pizza wheeled about for at least 30 seconds before rendering the waveform display for each track. And while the pizza is spinning, you're locked out of performing other operations. But on my G4, I could record audio and immediately start doing other things while the waveforms rendered.
Enough whining for now...
Tommy, exactly. It's nice to know how your tools work. When buying a computer or software, I don't think that anything concerning their operation should be left unexplained. But that's a lamentation for another day. In the meantime, it's great that this forum exists so Logic users can help each other out.

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Logical_Shift.vi ‏17 KB

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> Bavo.
>
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Will test.

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I am using a PXI 7853 and I for the past few days I have been playing around with using Memory blocks in the FPGA .
Now I am relatively new to Labview FPGA programming and hence I would be grateful if someone could provide me with clarifications on teh following :
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
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sbkr
Solved!
Go to Solution.

sbkr wrote:
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
When you compile the FPGA VI, it will include the values used to initialize the memory.
Are you asking what happens if you run the FPGA VI on your development computer, and your FPGA VI writes to the memory block, will the new values be included when you compile the FPGA VI? No, those values will be lost. The values that are included in the bitfile are the values that you used to initialize the memory block, as defined in the memory properties dialog box. The initial values are saved in the LabVIEW project file along with the memory block definition.
sbkr wrote:
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
You need to recompile the FPGA in order to use new initialization values, because those values are part of the FPGA bitfile.

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Dual Processors -- How Exactly Does Logic Use Them?

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