Erreur lors de compilation de l' FPGA

Question

bonjour, 
Voici l'erreur que j'obtiens quand je veux compiler mon programme FPGA
LabVIEW FPGA: La compilation a échoué à cause d'une erreur Xilinx.
Details:
ERRORack:2310 - Too many comps of type "SLICE" found to fit this device.
Design Summary:
Number of errors: 1
Number of warnings: 89
Logic Utilization:
Number of Slice Flip Flops: 7,963 out of 10,240 77%
Number of 4 input LUTs: 10,607 out of 10,240 103% (OVERMAPPED)
Logic Distribution:
Number of occupied Slices: 5,523 out of 5,120 107% (OVERMAPPED)
Number of Slices containing only related logic: 4,143 out of 5,523 75%
Number of Slices containing unrelated logic: 1,380 out of 5,523 24%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 11,028 out of 10,240 107% (OVERMAPPED)
Number used as logic: 10,454
Number used as a route-thru: 421
Number used as 16x1 RAMs: 70
Number used as Shift registers: 83
Number of bonded IOBs: 90 out of 324 27%
IOB Flip Flops: 97
Number of MULT18X18s: 38 out of 40 95%
Number of BUFGMUXs: 2 out of 16 12%
Peak Memory Usage: 359 MB
Total REAL time to MAP completion: 19 secs
Total CPU time to MAP completion: 19 
J'ai essayé de reduire mon programme le maximum mais l'erreur revien a chaque fois que j'ajoute une nouvelle variable
voici une capture ecran du programme 
merci d'avance
Pièces jointes :
Capture.PNG ‏39 KB
Solved!
Go to Solution.

Answer 1

Hi ramlus,
you know you posted in the English section of the forum?
To your problem: you have too much code to fit into your FPGA…
On your code:
- Why do you convert readings to SGL in the first place, when you have I16 indicators?
- Why don't you use FXP indicators?
- Why don't you scale the values in the RT host?
- Why don't you create an array of all measurement values and use just one array indicator to forward values to your RT host?
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome