ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard and ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

Question

I am attempting to follow the "after the out of the box" demo for the Zybo board. I am trying to generate a bitstream on vivado 2015.1 and I keep getting these two errors
ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 96 out of 226 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: gpio_rtl_tri_i[31:0], gpio_rtl_1_tri_io[31:0], gpio_rtl_0_tri_o[31:0].
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 96 out of 226 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: gpio_rtl_tri_i[31:0], gpio_rtl_1_tri_io[31:0], gpio_rtl_0_tri_o[31:0]
when first creating the project in Vivado 2015.1 i could not find the Zybo board in the list of boards to choose from. so i followed the "how to import Zybo board into project" topic located on the Xilinx community forum. Since i could not directly select the board some of the instrution for the demo had to be modified. In step seven i could not select the "apply board preset" box and in step 9 i could not assign "btn_4bits" and "sws_4bits" to the gpio blocks. The "After the box demo" can be found here
https://reference.digilentinc.com/zybo:gsg
Please help me with setting the I/O standards or importing the Zybo boards as one of the boards I can select insted of me selecting the properties of the board.
Thank you
 

Answer 1

Hi
As mentioned in the link (http://www.xilinx.com/support/documentation/user_guides/ug361.pdf), can you try the design with Vivado 2014.3?
Thanks,
Vinay