Everyone needs to check their Watch List and Forum Settings

Recently Sun's Java and Developer forums were consolidated into a single, large instance of the Jive forums infrastructure. Some users are no longer getting automatic email notifications on topics they have posted to. If your settings in Developer forums differed from settings in Java forums, then some settings may not be what you expect. Log into any forum, then verify your Forum Settings and Watch List options. In the Forum Profile and Settings, make sure your Watch List Preferances are correct, especially the Email My Watches Updates setting. In Your Watch List, make sure each topic has the Email Updates option set correctly.

Thanks for the info.
K

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    Hi All,
    Can any one let me know is the following requirement possible?
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    Regards
    Rajeev

    Hi Rajeev,
    You can try out both branch step and validation step and see which serves your purpose better.
    In branch step you can give multiple validation/validation groups,if result is TRUE take the first branch and check in at STOP.
    If FALSE,take dont checkin at STOP,either cascade or Rollback as the case be.Also here you can call the same or other Workflow.The split branches can later be combined using MERGE or Group.
    Other way can be by using Validation step,setup iteration threshold.here failed jobs will be sent to previous step and passed ones will move ahead in WF.Later you can checkin at STOP and failed jobs would still be in WF in checkout state.
    For your reference :
    http://213.41.80.15/SAP_ELearning/OKEC/nav/content/011000358700000601512007E.PDF
    http://help.sap.com/saphelp_mdm550/helpdata/en/43/e0615a82b40a2ee10000000a11466f/frameset.htm
    Thanks,
    Ravi

  • I need to check comparative three conditions and for each output I need to perform some action. can anybody please suggest

    I need to check three comparative conditions and for each status I need to perform some action. can anybody please suggest
    Requirment:
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    Easiest is suing an array of range boundaries, e.g. as follows:
    (Found here)
    Now it is fully scalable and  independent of the number of ranges. The solution in the earlier post would get complicated quickly whenever the number of ranges or boundary locations changes.
    LabVIEW Champion . Do more with less code and in less time .

  • Virtex6:Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings

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    PROGRESS_END - End Operation.
    Elapsed time =      0 sec.
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    // *** BATCH CMD : assignFile -p 1 -file "C:/Users/Administrator/Desktop/TEST/LED/led.bit"
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    1: VCCAUX Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
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    INFO:iMPACT:188 - '1': Programming completed successfully.
     Match_cycle = NoWait.
    Match cycle: NoWait
     LCK_cycle = NoWait.
    LCK cycle: NoWait
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    PROGRESS_END - End Operation.
    Elapsed time =     23 sec.
    Selected part: XCF128X
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    Current cable speed is set to 3.000 Mhz.
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    INFO:iMPACT - Verification string:  51 52 59
    INFO:iMPACT - Manufacturer ID:         49
    INFO:iMPACT - Vendor ID:              01
    INFO:iMPACT - Device Code:            18
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    Using x16 mode ...
    Setting Flash Control Pins ...
    Setting Configuration Register ...
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    '1': Start address = 0x00000000, End address = 0x008CE03B.
    done.
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    Using x16 mode ...
    Setting Flash Control Pins ...
    Setting Configuration Register ...
    INFO:iMPACT - Using Word Programming.
    '1': Programming Flash.
    done.
    Setting Flash Control Pins ...
    '1': Flash Programming completed successfully.
    Using x16 mode ...
    Setting Flash Control Pins ...
    Setting Configuration Register ...
    '1': Reading device contents...
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    Setting Flash Control Pins ...
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    `Elapsed time =    814 sec.
    and i find many people have met the same thing. But they are spartan  series FPGA and i try to low the Resistances of Mode pins,M0 M1 and M2, but the problem does not been solved.
    I have read the status Registers and find there is an over-temperature state 
    and in Impact i could not readback the registers. It is strange.
    I am anxious about this problem and have not solved it yet
    What reasons may it be?
    Hope for your answer, thank you

    Hi~I want to know if you solve the configuration problem for virtex-6?
    As I encounter the  same configuration problem, I want to consult  you with some question.
    Can I have your email?
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    I'd also suggest that you select the V6 in the JTAG chain view, then go to the debug menu of Impact and select Read Device Status (this is from memory, but it's something like that).  That will not only show the bits of the configuration status register, but also describe what each bit means.  Among other things you can check the state of the FPGA's configuration logic and the Mode pins.
     

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    --- When you hit a wrong note its the next note that makes it good or bad. --- Miles Davis

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