Feature Request: Song Controls in Coverflow and Bigger touch buttons

Something that really needs to be added to the iPhone software for the iPod are song controls ( |<< and >>| buttons) when the phone is resting sideways and in coverflow mode. I use the iPhone in my car as an MP3 player, and if it is in coverflow mode and I am listening to an entire Genre (on shuffle), there is no way skip forward to the next song - this also becomes a problem if I'm using an armband. It would be nice if Apple added forward/backward skip buttons in the coverflow mode.
Also - another concern is that touch-area around the song control buttons when you are NOT in coverflow mode isa bit small. When you are driving in a car, it actually becomes difficult to find the right area to touch (you know the >>| button) to skip to the next song. These would benefit from a small increase in size or just the touch area surrounding the button.
These seem like simple changes that can be easily implemented. Anyone else have these same concerns? Does anyone else have any other simple features that could be added to the iPod functionality to make it easier to use?
Message was edited by: dpbeardsley

Since this is a user to user help forum only for technical support issues and questions, best to use the iPhone feedback link for such feedback, which at least ensures that your feedback is forwarded to and read by the appropriate Apple personnel but does not ensure that your request will be implemented.

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    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    This thread has been closed and is continued in this new thread here: 
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    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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    1. If any post helps you please click the below the post(s) that helped you.
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    Join our BBM Channels (Beta)
    BlackBerry Support Forums Channel
    PIN: C0001B7B4   Display/Scan Bar Code
    Knowledge Base Updates
    PIN: C0005A9AA   Display/Scan Bar Code
    Solved!
    Go to Solution.

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  • Feature request: transplanting architectural state into OpenSPARC

    Hi All,
    This is a follow-up from our conversation at FCRC/ISCA last week.
    I have a feature request for the OpenSPARC RTL, and potentially the FPGA model, which would help researchers experiment with real workloads on OpenSPARC:
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    Ideally, this would happen over a socket so the transplant doesn't depend on a particular full-system simulator (e.g., we use Simics/Niagara at CMU, but I expect that many people would like to interface with SAM).
    I attempted this on my own a few months ago, with limited success. I wrote Verilog PLI/socket code that 1. slams many of the architectural registers and MMU and 2. replaces the interface in dimm.v with socket calls to a remote Simics instance (non-trivial code, has to reconstruct the phys addr and ECC bits to work properly). Much of this actually worked. I was not, however, able to redirect the core's PC to a new location and properly initiate an i-cache miss.
    Perhaps someone with a better understanding of the fetch/thread select stages knows the right combination of registers, valid bits, fetch/miss queue entries could make this work...
    Brainstorm:
    An alternative approach (which avoids many, but not all, dependencies on the specific RTL revision and is arguably superior to my first approach) might be to write a hyper-privileged "context switch" ASM routine to load architectural state and get the processor boostrapped at a new PC.
    This program could be like the usual validation test program, except it loads registers/MMU state from the hijacked DRAM model. Once these values have been loaded into the core, the caches can be invalidated to remove these temporary values (trivial with PLI code), and the full-system memory image can be enabled in the DRAM model.
    I can make my code available, if desired.
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    Jared

    Hi Jared,
    Thanks for following up on this.
    There could be wider interesting in this work and we feel that it makes a very good OpenSPARC based community project that can be hosted on opensparc.net.
    If you are interested in contributing the code and taking it forward then we can get it hosted and have right people from Sun help you in making it a successsful one.
    I will send you separate email on this topic.
    Thank You.
    Hi All,
    This is a follow-up from our conversation at
    FCRC/ISCA last week.
    I have a feature request for the OpenSPARC RTL, and
    potentially the FPGA model, which would help
    researchers experiment with real workloads on
    OpenSPARC:
    I would like to see a process for transplanting
    checkpointed architectural state of a booted and
    running T1000/T2000 system (arch. registers, MMU, and
    memory values) into the OpenSPARC RTL model.
    Ideally, this would happen over a socket so the
    transplant doesn't depend on a particular full-system
    simulator (e.g., we use Simics/Niagara at CMU, but I
    expect that many people would like to interface with
    SAM).
    I attempted this on my own a few months ago, with
    limited success. I wrote Verilog PLI/socket code
    that 1. slams many of the architectural registers
    and MMU and 2. replaces the interface in dimm.v with
    socket calls to a remote Simics instance (non-trivial
    code, has to reconstruct the phys addr and ECC bits
    to work properly). Much of this actually worked. I
    was not, however, able to redirect the core's PC to a
    new location and properly initiate an i-cache miss.
    Perhaps someone with a better understanding of the
    fetch/thread select stages knows the right
    combination of registers, valid bits, fetch/miss
    queue entries could make this work...
    Brainstorm:
    An alternative approach (which avoids many, but not
    all, dependencies on the specific RTL revision and is
    arguably superior to my first approach) might be to
    write a hyper-privileged "context switch" ASM routine
    to load architectural state and get the processor
    boostrapped at a new PC.
    This program could be like the usual validation test
    program, except it loads registers/MMU state from the
    hijacked DRAM model. Once these values have been
    loaded into the core, the caches can be invalidated
    to remove these temporary values (trivial with PLI
    code), and the full-system memory image can be
    enabled in the DRAM model.
    I can make my code available, if desired.
    Thanks!
    Jared

  • Coverflow and continous Hard Drive Spin - workaround

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    Hi jgregc,
    I have a brandnew IPod Classic with Firmware 1.0.2 and I followed your description. Yes, I can verify this exact behaviour. In addition I also tried to start listening to an album which I did not select with cover flow and the disc stops spinning after two or three seconds as it should.
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