FIR compiler 5.0 with DCM clock

Question

Hi all,
   I have a timing issue that usually goes away based on SmartXplorer cost table but I am curious as to why it even exists in the first place.  I basically have a differential 250MHz clock from an ADC that I deskew using a DCM.  The CLK0_OUT is then used to clock multiple things in my design, including a low-pass filter. I am confused as to why the reset logic is causing a timing issue to the low-pass filter.
Here is the error in my timing report:
Paths for end point peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk0000003e (SLICE_X99Y133.CIN), 11 paths
Slack (setup path): -0.679ns (requirement - (data path - clock path skew + uncertainty))
Source: ADC_V8_i/ADC_V8_DCM_i/FDS_INST (FF)
Destination: peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk0000003e (FF)
Requirement: 4.000ns
Data Path Delay: 2.386ns (Levels of Logic = 3)
Clock Path Skew: -2.138ns (0.523 - 2.661)
Source Clock: ADC_V8_i/ADC_V8_DCM_i/CLKIN_IBUFGDS rising at 0.000ns
Destination Clock: ADC_clk rising at 4.000ns
Clock Uncertainty: 0.155ns
Clock Uncertainty: 0.155ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.060ns
Maximum Data Path: ADC_V8_i/ADC_V8_DCM_i/FDS_INST to peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk0000003e
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
SLICE_X87Y132.AQ Tcko 0.450 ADC_V8_i/ADC_V8_DCM_i/FDS_Q_OUT
ADC_V8_i/ADC_V8_DCM_i/FDS_INST
SLICE_X93Y132.B6 net (fanout=2) 0.450 ADC_V8_i/ADC_V8_DCM_i/FDS_Q_OUT
SLICE_X93Y132.B Tilo 0.094 peripherals_i/generate_LPF.LPF_i/LPF_180/blk00000003/sig00000052
][11835_3592_INV_0
SLICE_X99Y132.A5 net (fanout=18) 0.755 ][11835_3592
SLICE_X99Y132.COUT Topcya 0.509 peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/sig00000056
peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk000004ae
peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk0000003a
SLICE_X99Y133.CIN net (fanout=1) 0.000 peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/sig00000088
SLICE_X99Y133.CLK Tcinck 0.128 peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/sig00000047
peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk00000037
peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk0000003e
Total 2.386ns (1.181ns logic, 1.205ns route)
(49.5% logic, 50.5% route)
 

Answer 1

 I actually have the timing report from a 0 timing score cost table on my local machine.  Is this helpful?
Slack: 1.778ns (period - min period limit)
Period: 4.000ns
Min period limit: 2.222ns (450.045MHz) (Tdspper_MULP)
Physical resource: peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk000000d0/CLK
Logical resource: peripherals_i/generate_LPF.LPF_i/LPF_0/blk00000003/blk000000d0/CLK
Location pin: DSP48_X0Y43.CLK
Clock network: ADC_clk