Flexrio FPGA dma and dram simulation

I have a pair of Flex RIO 7966r boards where I am trying to perform DRAM to DMA transfers. Each FPGA uses both banks of DRAM. One bank for capturing Camera Link frames, the other bank for capturing sub-frames from within each frame (And performing some processing on the sub-frame data).
Each DRAM bank is written into from their own target scopes FIFOs.
Each DRAM bank is read into their own target-to-host DMA FIFOs.
When only one side is operating or the other (Capturing sub-frames by themselves or full frames by themselves) everything flows nicely. But when I capture both at the same time, there appears to be some sort of contention in the DRAM (I suspect from the DMA engine). Since I am simulating all of this, I would like to ask if anyone has the detailed descriptions of the DRAM interface signals below? These are generated by LabView but I have found no explanation of what they mean in any documentation.
Also, in the simulation build, there is obviously a DMA simulation. But from within the simulator, I can find no signals related to the FPGA based DMA FIFOs or the simulated DMA transfers. All I can infer about the DMA transfers is the effect on the DRAM above. The DMA FIFO is being populated directly from the DRAM (Yes, this is a highly modified variant of the 10 tap cameralink (with DRAM) example from the NI-1483 examples).
Does anyone know how I can see the DMA bahavior from within a simulation? This would most likely allow me to see exactly why the contention is taking place.
Thanks!

Hey xl600,
I'm not immediately sure how to have ISim display the DMA Engine behavior, but I'll see if I can I dig anything up for you. I've come across a couple of other users encountering issues with FIFO signals appearing in ISim over on the Xilinx forums, so it might be worthwhile to post there as well in case it happens to be due to ISim itself.
Regards,
Ryan

Similar Messages

FPGA FFT and filtering

Hi, I have an application in which I need to collect a lot of (50+) narrowband spectral components from an analog input datastream. I am using a PXIe-7965R FlexRIO FPGA board and an NI-5732 digitizer adapter module. There are a couple of ways I could implement this, but I'm not sure which would be more efficient or plausible. The input datastream would be a 1D array of either 16kS or 32kS from the digitizer, and I would need to filter very specific frequency components out and sum them. Here are the options I was considering:
1. Take a Fourier transform of the data set, then generate a binary mask to multiply with the Fourier transformed result, effectively giving only the desired frequency components. The product array could then be summed for the final result. The main problem with this method is that I have not been able to find an FFT IP for LV FPGA that supports 1D input arrays longer than 8 kS. Does one exist? Additionally, there is the question of whether a longer FFT could fit on the FPGA.
2. Create a lot of time domain narrowband filters (Butterworth?) and sum the results of all of the filters. I am not sure if this would be less resources than the FFT or not. It would certainly be more cumbersome, considering I would have to implement 50+ filters on the input sequence.
I'm very new to LV FPGA and FPGAs in general, so I'd appreciate any comments or suggestions anyone may have for my application.
Thanks,
Ryan

Ryan,
I do not have any experience with FPGA so I am not addressing those aspects of your questions.
Have you verified that your numbers make sense? When I read your question my gut reaction was, "Can this even work?" "Is there enough data in 16 K or 32 K samples to extract that inforamtion?" What is the range of frequencies in the datastream? What is the sample rate? What is the required resolution? Can two or more components ever be closer together than the specified resolution? (Even if you do not care about resolving them in this case, which you cannot, overlapping signals might complicate the analysis). Are the frequencies of the components known? If so, are the frequencies rational fractions of the sample rate? Do any of the components vary in amplitude or frequency during one sample set?
I think that an FFT-based system will be the way to go. Multiple filters with narrow enough bandwidths would be a real mess, hard to get working well, and not versatile.
Lynn

FPGA DMA Size Allocation

Hi all,
My application involves grabbing images from a 3-taps, 16-bit camera using FlexRIO. The PXI controller I am using is Windows-based while the FlexRIO module that I have is a PXI-7954 + NI 1483 adapter. The size of the image I am grabbing is 2560 x 2160, U16 and the clock cycle is 100 MHz. I've been trying for over a week and up to today, I still am not able to get the image from the camera as I kept on getting the DMA Write Timeout error. Right now, the DMA size in the FPGA is set at 130k but whenever I tried to increase this further, I get a compilation error. I've tried to have the host program to grab 100k data points from the FPGA DMA at every milisecond but it seems that, I am capped at about 10-15ms. Perhaps, Windows has its own limitation...
Attached is the program that I am using, modified from the LabVIEW shipped example. Please advice, how do move forward from here? or, is it possible to further increase the DMA buffer size up 10x higher than the current limit?
Attachments:
1-Tap 10-Bit Camera with Frame Trigger.zip ‏1684 KB

Hi Shazlan
Apologies for taking so long to reply to you.
You are correct in saying that the latest driver is IMAQ 4.6.4 and this can be downloaded from our website if you have not done so already.
If you have already installed the IMAX 4.6.4 driver, has this managed to resolve your issue?
Also, have you tried to run the compilation again and obtained a report outlining the problems?
As a side note - I have been looking into the possibility of downloading some sort of driver for the Samos camera you are using from Andorra. While National Instruments have not created a driver for this device, Andorra do have a Software Development Kit (SDK) which they say works with LabVIEW. You may find it useful to have this so that you no longer have to write the driver yourself. This may then save resources on the FPGA.
Keep me updated on your progress and I will continue to look into this issue for you.
Regards
Marshall B
Applications Engineer
National Instruments UK & Ireland

CPU accessible registers in LabView FlexRIO FPGA

Howdy folks, I am wondering if it's possible to get the following behaviors out of Labview. I'm thinking it's not.
System description: CVI application that communicates with PXIe FlexRIO via controls and indicators.
Problem: Designing to a CPU-FPGA interface specification which lists "registers" as a combination of read and read/write bit-fields.
Example:
According to the spec, there should be a 32-bit register. Bits 31:16 are read-only, and bits 15:0 are read/write, from the perspective of the CPU. In the labview world, I would just make a uint16 control, and a uint16 indicator and be done with it.
However, to meet the spec (written for traditional microprocessor buses), a 32-bit read to an address should read back the full contents of the 32-bitregister at that location (implemented as flops on the FPGA, with appropriate memory mapping within the FPGA device). Similarly a 32-bit write to an address should store values to that register (appropriately masking writes to bits 31:16 within the FPGA device).
Is there a way for me to have a single address (basically, a single labview block diagram component) that will let me accomplish this behavior? It looks to me like the only solution is to pack my registers with bit fields that are all read, or all read/write in order to fit in with the labview paradigm. That means the spec will have to go back and be re-written and re-approved.
Thanks in advance,
-J
Solved!
Go to Solution.

Nathand,
Here is the standard paradigm (some simplification):
1) C helper file that contains #defines that describe the memory map. things like BASE_ADDRESS, DEV1_OFFSET, DEV2_OFFSET, REGISTER_1_OFFSET. To get to a
2) C procedure which calls things like void setRegister(uint32 *memory, int device_offset, int register, uint32 new_data, uint32 write_mask). and uint32 getRegister(int base_address, int device_offset, int register).
3) If I want to write the value 0xABCD the upper 16 bits of a 32-bit register (register 5), to device #1, I would code:
main(){
setRegister( ptrMemory, 1, 5, 0xABCD0000, 0x11110000)
This would compute the PCIe address based on some equation like BASE_ADDRESS + DEV1_OFFSET+register_offset<<2 (byte addressed).
Suppose this gives us a 32-bit address of 0xC000_4000. We would issue a write across PCIe to address 0xC000_4000. The memory map in the FPGA is programmed such that a set of flops will latch the data in the PCIe write when write_enable = 1, and address 0xC000_4000 are both true. That completes the register write to the FPGA.
A similar thing occurs for a register read. In this case however, when read_enable = 1 and address = 0xC000_4000, the values held in that same set of flip flops is now written onto the PCIe as a transaction. The software application recieves the value and returns that value from the getRegister function.
In my example above, you notice that the same address on the PCIe is used for reading and writing. I am trying to understand if I can have software read AND write from the same address.
When you compile an FPGA, labview creates a (seemingly) arbitrary address translation for all CPU accessible structures, meaning FIFOs, controls and indicators. It assigns different addresses for every single item, and it may or may not keep the same address depending on whether any modifications were done to controls/indicators/fifos since last compile.
I am trying to understand how labview works, so that I can assess whether or not I can read/write from the same address. This matters, because if I can pack bit fields into registers more efficiently in the FPGA, that reduces the amount of functional tests to write and execute to verify the FPGA functionality.
So, a restatement of my original question: is there some mechanism with using controls indicators where both the FPGA AND the CPU can write to the same set of flipflops in the FPGA? If I use an indicator, the FPGA can write to the indicator but the CPU cannot. If I use a control, the CPU can write to the control, but the FPGA cannot. Is this correct?
-J

Looking for Analog Out example using DMA and C++; cannot find sample "GenMultVoltUpdates_SWTimed"

Looking for example for Analog Out to multiple channels using DMA and C++. Found reference to sample "GenMultVoltUpdates_SWTimed" which I do not have and cannot find.

Hello Gerry,
When you install DAQmx, there is an option to install
support for Measurement Studio. When you
select this option, it will install these examples onto your hard drive. All of the examples can be found at the
following location: (C:\Documents and Settings\All Users\Documents\National
Instruments\NI-DAQ\Examples\DotNET2.0\Analog Out\Generate Voltage)
Respectfully,
Rob F
Test Engineer
Condition Measurements
National Instruments

HOST to FPGA DMA Transfers

Hi,
We're having trouble using the Host to FPGA DMA feature available in
LabVIEW 8.20 with IFRIO. After starting a compile, we get the following
error message:
An internal software error has occurred.
Please contact National Instruments technical support at ni.com/support
with the following information:
Error -61048 occurred at This target does not support DMA Output (from the host to the target).
Possible reason(s):
LabVIEW FPGA: This target does not support DMA Output (from the host to the target).
Any help would be greatly appreciated.
Thanks.

Hi Manik:
We did not support DMA output on the PCI-5640R when we released NI-5640R 1.0. This is why you are getting the error message that you are seeing.
We plan to add support for DMA output in an upcoming release.
----abhay

Fpga, Control and Simulation Module

Hello,
I am trying to implement control by Control and Simulation Module through NI CRIO 9024. The error message pops up when trying the run the RT vi.
Other vis which are not coded by the Control and Simulation Module can work properly. However, when it comes to the Control and Simulation Module, the error message pops up. Is there anything wrong with the installation of the Control and Simulation Module? Please let me know if you have an idea about that. I appreciate your help.

Hi Richard629,
As seen in this Knowledgebase article, you most likely do not have the Control Design and Simulation module installed on the controller. You can use NI Measurement & Automation Explorer to install the Control Design and Simulation module on your controller.
Regards,
Allison M.
Applications Engineer
National Instruments
ni.com/support

Communication problem between FPGA VI and Host-PC VI

Dear,
I am trying to set up communication between an FPGA an the host-PC using FPGA FIFO's.
The communication still has some problems and I don't know what would cause them.
Labview gives me the following reason "The transfer did not complete within the timeout period or within the specified number of retries."
What is wrong with my labview program? How can i solve this?
The Project can be found in attachment.
Best regards,
Jasper Beurms
Solved!
Go to Solution.
Attachments:
CEC20_02.zip ‏150 KB

Hello Jasper,
Are you fully familiar with how DMA FIFOs work on a cRIO?
Some general questions:
- Is there a specific reason that you need to use DMA FIFOs?
You seem to only require a 10 msec acquisition rate?
- Wouldn't it be easier to just use the Scan Engine in the case you don't need to go below 10 msec?
The Scan Engine should allow you to do acquisitions at this rate without even having to implement FPGA code yourself.
Another benefit is that the Shared Variables created/published by the Scan Engine are also by default visible over the network/
If want to use DMA FIFOs, then I would suggest you take a look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
I would advise that you read out the DMA FIFOs on a VI that is running on the RT Controller (RT VI) and then send those values from the RT VI over the network to your Windows VI.
You could use for example Shared variables to sent values from the RT VI to the Windows Host VI.
Another solution might be to use network streams or more custom TCP/IP communication.
If these concepts are new to you, then please have look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
This Guide should explain you all the basics you need to know.
If something is unclear or requires further explanation, then please let me know.
Kind Regards,
Thierry C - Applications Engineering Specialist Northern European Region - National Instruments
CLD, CTA
If someone helped you, let them know. Mark as solved and/or give a kudo.

Fpga DMA FIFO compilation error

Hello,
I have a cRIO 9074 with FPGA. I am trying a simple piece of code to learn how to aquire data that is generated on the FPGA at a rate of 10 KHz and transfer it to the Host VI for processing it later offline. However, I encounter this compilation error when compiling this basic FPGA VI containing a FIFO
write node (picture of the VI attached below). In the Compilation Report, it says that there were 256 Block RAMs used (the
total number is 40), therefore an error was produced. The exact compilation error
notification from the Xilinx report is reproduced below:
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow -timing toplevel_gen.ngd
toplevel_gen.pcf
Using target part "3s2000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
ERRORack:2310 - Too many comps of type "RAMB16" found to fit
this device.
ERROR:Map:115 - The design is too large to fit the device. Please check the Design Summary section to
see which resource requirement for your design exceeds the resources available
in the device. Note that the number of slices reported may not be reflected
accurately as their packing might not have been completed.
NOTE: An NCD file will still be
generated to allow you to examine the mapped design. This file is intended for evaluation use only,
and will not process successfully through PAR.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
Number of errors : 2
Number of warnings : 125
ERROR:Xflow - Program map returned error code 2. Aborting flow
execution...
Bitstream Not Created
Timing Analysis Passed
What does this mean? How can I fix this error?
Thank you,
Bogdan
Solved!
Go to Solution.
Attachments:
FPGA.png ‏16 KB

Sorry, I forgot to mention that...LAbVIEW 2009. And yes, this is the only loop on the FPGA.vi. I just made up this code to understand how exactly I would save some data on the host for subsequent processing, but I didn't get to that point because the VI on the FPGA does not compile successfully. Do you know of any example of the most basic code for DMA FIFOs between the FPGA and Host Computer? This should be pretty straight forward, but for some reason it's not.
Thanks,
Bogdan

Tick Count Express VI outputs '0' on FPGA target running with Simulated I/O

When I set my target to "Execute VI on Development Computer with Simulated I/O", the Tick Count VIs all output '0 every time they execute. How can I get them to output a progressive count (in the "ticks" instance) or a proper timestamp (in the "ms" instance)?
Solved!
Go to Solution.

I used LabVIEW 2013 SP1 and I was unable to reproduce this issue on my end. The screenshot below shows my result.
As shown on the Front Panel, the output from the Tick Count Express VI was not 0 on every iteration of the loop.
To make sure we are comparing the same code, can you reproduce this issue with the Tick Count shipping example? You can find this shipping example in the Toolkits and Modules>>FPGA>>CompactRIO>>Fundamentals>>Clocks and Timing>>Tick Count section in the LabVIEW Example Finder.
Regards,
Tunde S.
Applications Engineer
National Instruments

High Speed Streaming with Multiple FPGA FIFOs and TDMS Advanced Asynchronous (Data Ref)

I am using an FPGA with adapter card (7962 with 5751) for data acquisition and signal processing. I have adapted the FlexRio example "High Throughput Streaming," which works very well for a transferring data from the FPGA via a single FIFO. This example uses the TDMS Advanced Asynchronous Write (Data Ref). The "High Throughput Streaming" example is similar to "Streaming External Data to a TDMS File (Windows)" but includes more code to prep the FIFO buffer size and TDMS size.
My question is how can I adapt this code to incorporate multiple FIFOs that write data to different channels in the TDMS file? Can I use multiple instances of TDMS Advanced Asynchronous Write (Data Ref) in a single VI for each FIFO Acquire Read Region? If so, how do I insure that the correct data is written to the correct channel in the TDMS file?

Thank you DeppSu for your explanation, I will look into that.
But first, I want to be sure that the FPGA and the Hot general designs are correct, which for the moment I am not sure. So I have included my code.
I tried the Host vi several times, and it seems that it works sometimes and sometimes not, like there are some communication problems between the fpga and the host on the "read acquire region" method which is not executed. I managed to make it work randomly before, but not now. Maybe it is because of the reset that I added?
If someone could check my code and help me, I would really appreciate it since nobody in my workplace has the expertise to do so :-) If you see some obvious mistake, please share with me, I also added some comment boxes in the code with questions.
Delphine
Attachments:
thoughput.zip ‏1261 KB

Labview 8.0 FPGA DMA question

I am developing a control system which needs to access a big mass of
variable data (32 Mbyte) that i can put into the host computer RAM. In
labview tutorial and also on other web resources it is well described
how the DMA FIFO can be used to "write to" host PC memory (RAM) but
nothing about "reading from" the PC RAM. Is it possible? And which is
the control to be used? Do I need some lower level coding?
Thanx
Davide

Hi Davide,
As of right now, the DMA transfers are one-way only (FPGA to host).
Best regards,
David H.
Systems Engineer
National Instruments

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator. The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project. There are, however, several issues/questions we
have. Attached are the HOST and FPGA vis that we are working with.
1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

Is there a single snmp oid for flash and dram ?

Does a single univeral oid (or 1 for flash and one for dram) exist that will provide total amount of flash and total amount of dram across all chassis families ?
Thanks

This link is your best bet:
http://www.cisco.com/warp/public/477/SNMP/contiguous_memory.html

How to make my waveform in control and design simulation run continuously?

Hi all, i m a begineer of Labview and have some question to ask.
I am using the Labview to design and implement a controller for FOPTD system, but i found that the waveform in the "control and simulation loop" is not running continuously. I mean it keep repeat in the same graph from 0 to 10second. Is there any approach to make it run continuously?
Thankyou very much.
Solved!
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Attachments:
Project 1.png ‏12 KB
Project 2.png ‏18 KB

Well, my suggestion then is to do the following: change final time from Inf back to 10 s (or whatever number that capture the whole simulation) and do a while loop around the Control and Simulation Loop with a "wait until next ms" function to give you time to react and change parameters, like this below. This would make LabVIEW to do the whole simulation, wait for 1000 ms and then, run the simulation again with new parameters. If you need more time, just need to change the constant wired to the "wait until next milisecond".
Barp - Control and Simulation Group - LabVIEW R&D - National Instruments

Flexrio FPGA dma and dram simulation

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