FPGA Xilinx compilation failed. Access to the path 'C:\NIFPGA\corecache\activity.log' is denied.

I have just rceived my cRIO.  I have installed all the necessary software and drivers and have written a VI in FPGA mode.  However, when I try to compile the code I get the follow error message (see attachment).  I have contacted NI support and they have been unable to solve this proble as of yet.
The NI engineer gave me the following advise:
1. Launch the Registry Editor by selecting Start » Run and then entering regedit in the Run window.  
2. Press the Enter button to open the editor. 
3. Find the following registry key in the path below:  
HKEY_LOCAL_MACHINE\SOFTWARE\Wow6432Node\National Instruments\LabVIEW\11.0\AddOns\FPGA\CompilerPath_Xilinx12_4 
* the Wow6432Node may not be correct in all cases. on my PC, you go to HKEY_LOCAL_MACHINE\SOFTWARE|National Instruments\LabVIEW\11.0\AddOns\FPGA\CompilerPath_Xilinx12_4 
4. Under the Data Tab, you should see the path that your CompilerPath_Xilinx12_4 is linked to. Please confirm that it is linked to C:\NIFGPA\programs\Xilinx12_4 
If you have Xilinx 11.5 installed, make sure it also is linked to the proper path. 
5. If you have previous versions of LabVIEW installed, you will have to go to those versions as well. For Example if you have LabVIEW 2010 installed, please go to 10.0\AddOns\FPGA 
Make sure that the CompilerPath_Xilinx12_4 or CompilerPath_Xilinx11_5 or CompilerPath_Xilinx10_1 are all correctly placed under the C drive as well as seen above in step 4. 
6) Make sure that the "Working Directory" under LabVIEW 11.0 has the correct path of C:\NIFPGA\ 
7) After this, close otu the Registry Editor and navigate to where the FPGA Compile Worker is located. By default it should be here: C:\Program Files (x86)\National Instruments\FPGA\CompileWorker 
8) In here open the "WorkerRootDirectory.txt" document and change the path. Make sure that it points to the C Drive. 
9) Save and close the file. Restart your computer.
All of this was already correct and still cannot compile.  
Solved!
Go to Solution.
Attachments:
FPGA.png ‏131 KB

Usually, an "Access to the path ... is denied." error stems from user permissions.
What Operating System are you using?
Are you using this tool from an administrative account?
Is there a custom security policy on your workstation that dictates user rights and permissions?
Is it possible to run LabVIEW as an administrator?  (ex. in Windows 7, you would right-click on LabVIEW.exe and select "run as administrator.")
Best regards,
Matthew H.
Applications Engineer
National Instruments

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  • "LabVIEW FPGA: The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD

    The compilation of my labview fpga vi fails with the error message "LabVIEW FPGA:  The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD".
    In the 'final timing (place and route)' report, the requested frequencies are all below the maximum frequencies and the compilation error message is only displayed at the very end on the 'summary' page.
    I tried to optimize my labview fpga vi with pipelining, but had no success.
    Can anybody offer some advice on how to debug fpga code with this error? Is this really a timing error or something else?
    Software:
    Labview 2011, fpga 2011, xilinx tools 12.4 sp1
    Hardware:
    NI PXIe-1071 Chassis
    NI PXIe-8108 Embedded controller
    NI PXIe-7965R FPGA FlexRIO FPGA module
    NI 5761 250 MS/s 14 bit Analog input digitizer
    The Xilinx log of the compilation run is attached.
    Also, this issue was already discussed in this thread ~6 months ago, but no satisfying answer was offered so far...
    Thanks,
    Fabrizio
    Attachments:
    xilinxlogc.txt ‏2313 KB

    Hi Kyle,
    the problem is: I have one computer which compiles the VI successfully and a second one which shows that error. Both use the same software setup (LV2011SP1+RT+FPGA from DS2012-01). Both use the same project file - atleast SVN shows no difference.
    - You can have one FPGA VI where one computer is compiling successful and a second one complains. (Btw. I have a SRQ running in Germany on this topic.)
    - More problems: After successful compiling on first computer and transferring all to second computer (using SVN, including the full project folder with all files like bitfiles, lvproj, and everything) the second computer is unable to start the RT executable due to error "FPGA VI needs to recompile". Solution so far: Call the FPGA-OpenReference with the bitfile instead of the VI (as I used to do until now)...
    - More problems: After modifying the FPGA-OpenReference to use the bitfile (on the 2nd computer) and transferring all the files back to the 1st computer (using SVN as before, including the whole project) the 1st computer complains: FPGA-OpenReference is creating a different reference than is used in the VI. So what happens here? On one computer my VI is ok, the reference is typed correctly. Transferring all the files to a different computer the VI isn't ok anymore due to changes of the reference??? You know: all files are the same: lvproj, FPGA bitfile didn't change, cRIO reference didn't change...
    All those problems didn't occur on my RT-FPGA projects in LV2010SP1. I'm not pleased...
    Best regards,
    GerdW
    CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
    Kudos are welcome

  • LabVIEW FPGA: The compilation failed due to a xilinx error

    I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
    Details:
    ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
    INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
    ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
    VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
    -->
    Total memory usage is 204688 kilobytes
    Number of errors : 2 ( 0 filtered)
    Number of warnings : 4 ( 0 filtered)
    Number of infos : 0 ( 0 filtered)
    Process "Synthesize - XST" failed
    Compilation Time
    Date submitted: 2014/2/26 18:15
    Date results were retrieved: 2014/2/26 18:17
    Time waiting in queue: 00:06
    Time compiling: 02:02
    - PlanAhead: 01:16
    - Core Generator: 00:00
    - Synthesis - Xst: 00:35
    Solved!
    Go to Solution.

    I have got the same error, Have you solved this error?
    What you have done?
    jasonneu wrote:
    I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2013.The code had compilated successfully in labview2012. Any suggestions on what is causing this issue?
    Details:
    ERROR:HDLCompiler:432 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 29: Formal <cparametersignal> has no actual or default value.
    INFO:HDLCompiler:1408 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaSetOutputDataEnable.vhd" Line 37. cparametersignal is declared here
    ERROR:HDLCompiler:854 - "C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd" Line 21: Unit <vhdl_labview> ignored due to previous errors.
    VHDL file C:\NIFPGA\jobs\THY4t7n_z6im2K7\NiFpgaAG_0000003a_SequenceFrame.vhd ignored due to errors
    -->
    Total memory usage is 204688 kilobytes
    Number of errors : 2 ( 0 filtered)
    Number of warnings : 4 ( 0 filtered)
    Number of infos : 0 ( 0 filtered)
    Process "Synthesize - XST" failed
    Compilation Time
    Date submitted: 2014/2/26 18:15
    Date results were retrieved: 2014/2/26 18:17
    Time waiting in queue: 00:06
    Time compiling: 02:02
    - PlanAhead: 01:16
    - Core Generator: 00:00
    - Synthesis - Xst: 00:35
    Mahran

  • FPGA Compilation fails with Xilinx "Block Memory Generator 8.1" configured with a Coefficient File

    Hello All,
    I have a SubVI that uses block memory, which has been created using Xilinx "Block Memory Generator 8.1". I have configured this block memory to be a "Single Port ROM", and I use a coefficient file to initialize the memory contents. In simulation mode, everything works as it should.
    Next, when I try to compile the top-level VI, I get the following error:
    http://www.cs.nyu.edu/~aditya/Compilation_Log_100.txt
    http://www.cs.nyu.edu/~aditya/Dividing (This is the coefficient file)
    Essentially, the compiler is looking at an ill-formed path to find the coefficient file.
    My environment:
    -- LabView 2014 f1 (32 Bit)
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    -- Xilinx Vivado 2013.4
    -- NI RIO Drivers 14
    -- Development Machine and Conpile Server: Windows 7 Professional, 32GB RAM
    -- Compile Worker running Linux, with Xilinx Compile tools installed
    Is this a bug, or am I doing something wrong? Thanks!
    Best,
    Aditya

    Next, I tried compiling on the windows machine itself. And here is the error that I get. (See attached image).
    Thanks!
    best,
    aditya
    Attachments:
    Capture.PNG ‏18 KB

  • LV2013 FPGA Linux Compile Worker errors (Xilinx 14.4)

    Hi,
    Until today, we had a nice working LV2012 Win7 and Xilinx 13.4 Linux Worker remote compilation system.
    Necessity mandated an upgrade to LV2013 FPGA for Win7. Which mandated a Linux distro upgrade to RH6.3x64 per the documentation.
    Now, our FPGA code won't compile successfully on the Linux Worker 14.4 x64, but will succeed on Win7 local worker.
    Enclosed are our xilinx.log file and a terminal capture .txt of the compilation errors from Linux Compile Worker run.
    Installation had no errors or warnings, and the Linux Compile Worker connects to the Win7 Server successfully.
    Please help, as without this optimization our code compile times are 2-3x longer.
    Our FPGA is NI-7962 FPGA (Vertex 5)
    Thanks,
    John
    Attachments:
    XilinxLog.txt ‏61 KB
    xilinx14.4_terminal_spew.txt ‏16 KB

    Thanks for getting back with more tests. The TCL prompt didn't evoke any errors and returned a friendly "hello" using puts hello.
    Attached is the output from xinfo.
    Note that the path to these files is slightly different than what you provided:
    /usr/local/natinst/NIFPGA/programs/xilinx14_4/ISE/bin/nt64/xtclsh
    mine is:
    /usr/local/natinst/NIFPGA/programs/xilinx14_4/ISE/bin/lin64/xtclsh
    /usr/local/natinst/NIFPGA/programs/xilinx14_4/common/bin/xinfo
    mine is:
    /usr/local/natinst/NIFPGA/programs/xilinx14_4/common/bin/lin64/xinfo
    Best,
    John/Carskie
    Attachments:
    xinfo.txt ‏57 KB

  • Does the Xilinx compiler "learn" from past compilatio​ns?

    Hi all,
    I noticed that if I have piece of FPGA code that is close to meeting timing, after I can get it to compile once, by trying the compile multiple times, it will keep compiling on subsequenct builds as I modify parts of the code not in the path of the code that was causing the violation. 
    I also jsut upgraded to LabVIEW FPGA 2014 and the latest xilinx tools (14.7 ISE) from LabVIEW FPGA 2012 and my compiles take way longer and is not meeting timing, on the same code. Is this because I just flushed all the old data from previous compiles?

    Hey qfman,
    Every time you compile the resource mapping starts from scratch so I believe this is most likely a "chance" behaviour you are seeing. Between LabVIEW FPGA versions there are different compiling algorithms/overhead which might come into play for the timing or resource allocation during compile. As far as LabVIEW FPGA 2014, are you using your own computer or the Cloud Compile to compile the code? I'd recommend trying the Cloud Compile (http://digital.ni.com/public.nsf/allkb/C272BBA0A69​59DB6862578DB00808AC3) and seeing if you get the same behaviour.
    Hope this helps!
    Xavier
    Applications Engineering Specialist
    National Instruments

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