High-level interrupt handler

Why can I decide to support a high-level interrupt or not? Under what condition does the Solaris kernel will map my hw interrupt (INTA from PCI bus) to a high-level interrupt? When should I refuse to support a high-level interrupt? Why? Can I force my hw interrupt to be a high- level interrupt?
Also think about that, most hw interrupts indicate something important such as the case buffers are full. If they are assigned below the scheduler's, it really does not make sense.
Is it possible to block any hw interrupts? Or I'd put it this way can I prioritize hw interrupts in Solaris?
Thanks
tyh

Hi,
On x86 each IRQ has a software priority assigned to it implicitly by the bus driver, although I think you could override it in the driver.conf. Unlike SPARC, the processor doesn't support a PIL so software priorities are implemented by masking all lower-priority IRQs and re-enabling interrupts.
High priority interrupts, above dispatcher level, run in the context of the current thread on the cpu, normal level interrupts are handled by interrupt threads.
The interrupt threads are the highest priority threads on the system, so will preempt any other running threads. In addition mutexes in Solaris use priority inheritance, so the interrupt threads will get to run.
In general, high level interrupts are allocated to devices with small buffers such as serial or floppy, so that their buffers get serviced in the fastest possible time. Others can afford to wait for just a bit.
Your driver should check to see if its device has been allocated a high level interrupt. If this is the case, the high level handler should clear the interrupt and save the data/status (in the driver state structure perhaps) and trigger your soft level interrupt handler (which will run as a thread).
Blocking of interrupts is done for you when you acquire a spin mutex (ie initialised with an iblock cookie). Such a mutex is required to synchronise access to data shared with a high level handler in your driver.
Please take a look at the Intel Driver writers orientation at:
http://soldc.sun.com/developer/support/driver/docs/Solaris_driver_models/index.html
Hope that helps,
Ralph
SUN DTS

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    case PCI_CLASS_MASS: /* Mass storage Controller class */
    return 5;
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    return 6;
    case PCI_CLASS_DISPLAY: /* Display Controller class */
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    case PCI_CLASS_MM: /* Multimedia Controller class */
    case PCI_CLASS_MEM: /* Memory Controller class */
    case PCI_CLASS_BRIDGE: /* Bridge Controller class */
    return 12;
    Don't know why sun has deciced that multimedia, memory
    and bridge pci controllers must have an IPL 12 (= hi level
    interrupt). The solution is indeed to add an
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    around this problem and get rid of the hilevel interrrupt.
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