HLS IP with multiple outputs

Question

Hello all,
I'm currently working with Vivado HLS (2014.4) and am trying to generate an IP with has an generic amount of OUTputs.
For better explanation I've made an "block-image" (sort of) how it should look like when imported in Vivado (in a Block Design):
So it gets an array of booleans (preferable generic!) and splits it into "sizeof(bool[])" output signals.
What I mean with generic is showed in the following picture:
This is the "utility vector logic"-IP from Vivado. There you can set, if double-clicked, the parameter "CSIZE" which directly sets the size of in- and output arrays to CSIZE.
I'm trying to achieve something similar:
I want to Input an array  "in[CSIZE]" and split it into CSIZE output wires!
Best would be if i would be able to set the parameter CSIZE of my synthesized IP in Vivado, the way it's done in the "utility vector logic" - IP through the Properties menu.
1) Is this even possible with High Level Synthesis?
2) If not: Is it possible with a fixed size input array (like in[5]) and then manually set the number of output wires to e.g. 5?
3) If this is too isn't possible: How does is work to output a boolean array ("Res[9:0]") like it's done in the "utility vector logic"-IP?
3.1) Which directives would i have to use to achieve this goal?
Because right now, I don't know how to output a boolean array as signal (it always changes to memory, or if implemented as Pointer it's no output (it's on the left side)
It should look something like this (analog to "utility vector logic"):
where in and out are boolean ports.
Preferable the size of the in- and output array is generic and settable in the Vivado properties menu (like mentioned in the example above)!
4) Could you give me according c++ code snippets to solve my problems and to achieve my goal?
My goal is to connect multiple own IP's (theirs clock) with the multiple output ports of the generated IP above (therefore multiple outputs).
I'm grateful for every answer I get!
Thank You very much!
Best regards,
Tilo

Answer 1

Hi
You can't use VHLS to get an IP with parameters;
To be optimal, a change of parameter would need the generated RTL to change, and at the moment, if you wanted to change your IP then you need to rerun C-synthesis. In other words, VHLS doesn't generate IPs with parameters.
For the other question , check the use or array partition complete;
Be aware that outputs have a valid driven interface by default - that's because the outputs may not be valid at every clock cycle when the IP is running.
An example of what you described might be this clock divider that generates N outputs where gen_clk[i] is input clock divided by (M/rate[i])
const unsigned int n_outputs = 5;
void top(unsigned int M, unsigned int rate[n_outputs], bool gen_clk[n_outputs]) {
#pragma HLS array_partition variable=rate complete dim=0
#pragma HLS array_partition variable=gen_clk complete dim=0
#pragma HLS interface ap_none port=gen_clk
#pragma HLS pipeline
unsigned int i;
static unsigned int counter[n_outputs];
static bool int_clk[n_outputs];
for(i=0;i<n_outputs;i++) {
// pipeline (II=1) at top level makes this loop unrolled
bool clk_enable = counter[i]>M;
int_clk[i] ^= clk_enable;
counter[i] = clk_enable ? counter[i]-M: counter[i]+rate[i];
gen_clk[i] = int_clk[i];
but be aware that the tool tells you clearly:
@W [RTGEN-101] Port 'gen_clk_0' with mode 'ap_none' may require an associated data valid signal to correctly communicate with other blocks or a test bench; automatic C/RTL co-simulation may not be able to verify such a port.
In IPI you may not be able to integrate this as the outputs are not decorated as being of type "clocks".
I hope this helps.