How can I control individual pins of VHDCI connector on PXIe-6548?

I need to use the VHDCI interface on slot 3 i.e. NI PXIe-6548 of NI PXIe-1062Q for testing purposes. I need to raise or lower the individual lines from the available 68 lines. Do I need to use VISA to do so?
If not VISA, how do NI-HSDIO VIs that are availble with LabView 2009 help to do so? The MAX test pannel specifies channel 0-15 and 16-31. How are these channels related to the 68 lines?
Solved!
Go to Solution.

Thanks Keith!
I still have some problems. I appreciate every bit of your help.
How does the in-built ni HSDIO VI take care of the parallel communication protocol. e.g. There are some pins as chip-select, Rd/xWr etc. they need to be raised or lowered according to the operation. Now, I am trying to communicate with the DUT using 9 bit data, 9 bit address.
I tried to write in the DUT using static generation VI. I formed a word of 20 bits according to the mapping of 9 address, 9 data, a chip-select and a RD/xWR and generated that word on the channels 0-19.
But when I tried to read data from DUT, It acquires the same data that was written on 0-19. For a read operation, the active-low chip select is lowered after the rising edge of the clock, RD/xWR is raised, and the respective address lines are raised, then on the next positive edge of the clock the data is sampled. I do not understand how to make all of this happen using Labview. Instead of reading back from the DUT, the VI gives me the same pattern that I generated.
I know how the parallel communication is supposed to happen, but I don't understand how LabView is supposed to be used for this.
Please help.

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