How do I file Bug Report? Labview FPGA

I'm not sure if this is a software bug or what, but I'm trying to run the Analog Input example project for Labview FPGA , in "Find Examples >> Hardware Input and Output >> R Series >> Basic IO >> Analog Input - R Series".
The thing is, it works.. mostly.. I manage to send in a sine wave, and see it. However, every now and then, when I set teh Waveform Graph X-axis to autoscale, and change the Update Mode, every time I put it into mode Scope Chart, it freezes my computer, and I have to physically power off my computer and power it back up (which i'm not happy about). I'm using the default settings for the example, my card is in RSE mode, input signal at 25 Hz, 4V p-p
I doubt anyone can guess why this is happening, but is there any way to file a bug report?
Thanks,
Hardware: Quad-core Xeon 2.33 Ghz, 8 GB RAM, PXI-7583R FPGA, PXI-1036 Chassis
Software: Labview 8.6.1, LAbview FPGA 8.6., Vista 64-bit
NI Hardware: PXI-7853R, PCI-5122, PCI-6733, PXI-1036, PCI-MIO-16E-4, PCI-6110
Computer Hardware: Xeon Quad Core - 2.33 Ghz, 8 GB RAM
Software: Labview 2009, Labview FPGA 2009, Vista 64-bit, MAX 4.6, DAQmx 9.0, NI-SCOPE 3.5

1... Adding an unrelated question to a 3-month old post is not the best way to get your questions answered.
Start your own thread next time.
2... The example works fine for me. The EQUALS function works just fine for strings. Be aware of some things, though:
Case matters. If you want to ignore case, then uppercase both strings (or lowercase them) before comparing.
Length matters "X" is not the same as "X ". "123" is not the same as "1234".
Steve Bird
Culverson Software - Elegant software that is a pleasure to use.
Culverson.com
Blog for (mostly LabVIEW) programmers: Tips And Tricks

Similar Messages

How do you file bug reports for iBooks?

There is no such option at the following URL.
http://www.apple.com/feedback/
Thank you in advance.

You can use the feedback for whatever device you are using the app on, and also the feedback for iTunes.

How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
   input in1,in2;
   output reg out1;
   always@( in1 or in2)
   begin
      out1 <= in1 & in2;
   end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
    port (
        in1    : in std_logic;
        in2    : in std_logic;
        out1   : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
   port(
         in1    : in std_logic;
         in2    : in std_logic;
         out1   : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
   port map(
            in1 => in1,
            in2 => in2,
            out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd"    Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type   'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol   "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

How to submit a bug report for OSB? - restore fails if number of items per page is changed from the default of 30

In the OSB web gui, one of my users found that if the number of items per page is changed from the default of 30, the restore of the file will fail. He tested this using recent versions of Firefox and IE. We have verified this to also be the case using Chrome.
In a directory containing over 100,000 files, moving 30 at a time to find the one to be restored is a very frustrating user experience.
How do I file a bug report for this issue? Is there a workaround for this bug to enable my users to more easily find the file to restore without being restricted to the default of 30 items per page?

Yes there is a bug in the webtool in the current release. You can use the commandline obtool to do the restore, that is much faster and works fine.
Thanks
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How to simulate external hardware in LabView FPGA ?

Hello,
I have a NI 7952R connected to a 6583 IO module.
This IO module is connected to a digital sensor that continuously sends patterned data.
I am developping the code for the FPGA and I would like to know how to perform a cycle accurate simulation of the whole system.
There is an example for a cycle accurate simulation of the labView -> FPGA interface, but it doesn't include the behavior of an external hardware connected to the FPGA IO module.
Now I have a VHDL simulation model (not synthetisable) that describes my sensor. How to include that into the iSim cycle accurate simulation?
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Thank you for your answer, I think now we have a common understanding of your intent.
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Taken from:
Introduction to Cycle-Accurate Simulation
http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_simulation_intro/

How exactly does the memory in Labview Fpga work

I am using a PXI 7853 and I for the past few days I have been playing around with using Memory blocks in the FPGA .
Now I am relatively new to Labview FPGA programming and hence I would be grateful if someone could provide me with clarifications on teh following :
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
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I tried testing with simulation for FPGA VI and found that when i try to change the memory values by running the initialization VI . a pop up comes that says that it is not possible as the FPGA VI is still in use .
Any light on this or guidance with links would be highly appreciated
Cheers
sbkr
Solved!
Go to Solution.

sbkr wrote:
a) Since I am working on the development host computer when I initialize the Memory with the option of using a Memory initialization VI then how does it exactly happen in the backend .What I mean to ask is , when i change values of memory in the development computer and then compile the FPGA VI into the board ,is it that the Memory information is ported into the FPGA .If this is the case then in what form are the details initially saved in the development computer .
When you compile the FPGA VI, it will include the values used to initialize the memory.
Are you asking what happens if you run the FPGA VI on your development computer, and your FPGA VI writes to the memory block, will the new values be included when you compile the FPGA VI? No, those values will be lost. The values that are included in the bitfile are the values that you used to initialize the memory block, as defined in the memory properties dialog box. The initial values are saved in the LabVIEW project file along with the memory block definition.
sbkr wrote:
b) Is it possible for me to use the initialization VI method to change the valuesi n memory while the FPGA VI is running .If not ,then would it make a difference if I stop the VI and then change the values using initialization method .Would that actually reflect on the FPGA or should I have to re compile the FPGA VI every time I change the memory values in the development computer using the 'Initialization VI method ( that is available as an option when we right click on the memory block in the project explorer window )
You need to recompile the FPGA in order to use new initialization values, because those values are part of the FPGA bitfile.

How can I install (download) a Labview FPGA code onto Altera FPGA chip using Labview FPGA module?

Hi there
Guys i'm a very new labview user (PhD student), my project is about ( design and implementation of a high speed-yet sophisticated system using Labview environment then install this project's code (using Labview FPGA module) onto Altera-made FPGA chip).
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as previously mentioned, labview fpga only supports national instruments targets utilizing xilinx fpgas. the hdl generated by labview fpga is encrypted and cannot be used to synthesize a design outside the labview fpga design flow.
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How about fixing the bug report submission page ?

I've been trying for I think the 11 time to submit a bugreport to bugreport.sun.com and each time,
the submission FAIL. And of course you loose everything you entered in the page.
Email to the address specified when it fail also FAIL.
rejected by the server for the recipient domain sun.comby userp1020.oracle.com. [156.151.31.79].
The error that the other server returned was:
550 5.1.1 <[email protected]>... User unknown
Please Fix, a bug report page that can't even submit simple text its ridiculous.
This is not the first time I have difficulties getting your site to work.

You're complaining to the wrong people.
Re: bug database does not work?
OTN forum admin are not responsible for the java bug reporting. They cannot fix what isn't theirs.
Locking this thread

How to do a bug report when firefox doesn't crash ?

Hello everybody,
I have Firefox nightly since a long time now. But since the beginning of the week, I've got some issues with it. New packages doesn't changed anything.
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I would suggest first of all that you try using a normal release of Firefox. It is easy to use both an ordinary release and another version of Firefox on the same computer,post again if you need help with that.
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What is your first language?

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Is there someone to contact; or, is there a way to find out the disposition of a bug report which has possibly not been assigned a number yet, or whose subject has been changed (i.e. can't be found in a search) ?
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Seems like a search of the bug report submission
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Where can I file bug reports?

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Hi,
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Find Control in Event Structure doesn't show the object when it is not in the frontmost Tab page [Bug Report, LabVIEW 2012]

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The result is that the control/indicator is highlighted on the FP. The problem is, if that control is in a Tab and specifically in a page of that Tab that happens to not be the frontmost, the only thing you'll see is marching ants, but no control:
<=========== the wrong TAB page was shown. LV did not bother to switch to the relevant one....
In other words, "Find Control" in the Event Structure doesn't switch the tab to the owning page. This is contrary to what happens if you right-click, say, the terminal of this control: the FP will switch to the owning Tab page.
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I did not. Is there any better chance for it to be caught there by a NI eye than it is in the LV forum? I though these threads were deemed to gather bugs/features that had been already acknowledged by NI with a CAR number.
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Where to file bug reports with Desktop Intelligence?

Hi,
Is this the right place to make report bugs on Desktop Intelligence?
Regards.

Hi Florian,
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Regards,
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Solaris8 and 9 (possibly 7) /dev/poll driver bug report.

Hello,
I'd like to report a bug in the solaris 8 and 9 /dev/poll driver (poll(7d)).
As i do not have a support account with sun or anything like that, there
seems to be no other way to do that here (which is of course a very sad
thing).
Bug details:
The /dev/poll device provides an ioctl-request (DP_ISPOLLED) for checking
if a particular filedescriptor is currently in the set of monitored
filedescriptors for that particular /dev/poll fd set (open /dev/poll fd).
A quote from the documentation of the poll(7d) manual page taken from
Solaris9:
"DP_ISPOLLED ioctl allows you to query if a file descriptor is already in
the monitored set represented by fd. The fd field of the pollfd structure
indicates the file descriptor of interest. The DP_ISPOLLED ioctl returns 1
if the file descriptor is in the set. The events field contains the
currently polled events. The revents field contains 0. The ioctl returns 0
if the file descriptor is not in the set. The pollfd structure pointed by
pfd is not modified. The ioctl returns a -1 if the call fails."
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monitored in the set, that it would return 1, and change the events field of
the pollfd structure to the events it's currently monitoring that fd for.
The revents field would be set to zero.
However the only thing which actually happens here, is that FD_ISPOLLED
returns 1 when the fd is in the set and 0 if not. When the fd is in the
set, when FD_ISPOLLED returns 1, the events field remains unmodified, but
the revents field gets changed.
A small sample code to illustrate:
#include <stdio.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/devpoll.h>
main() {
struct pollfd a;
int dp_fd = open("/dev/poll", O_WRONLY);
a.fd = 0; /* stdin */
a.events = POLLIN; /* we monitor for readability, POLLIN=1 */
a.revents = 0;
write(dp_fd, &a, sizeof(a));
a.fd = 0;
a.events = 34; /* filled in with bogus number to show malfunctioning */
a.revents = 0;
printf("DP_ISPOLLED returns: %d\n", ioctl(dp_fd, DP_ISPOLLED, &a));
printf("a.fd=%d, a.events=%hd, a.revents=%hd\n", a.fd, a.events,
a.revents);
According to the documentation of /dev/poll and namely DP_ISPOLLED this
program is supposed to print the following:
DP_ISPOLLED returns: 1
a.fd=0, a.events=1, a.revents=0
However it prints the following:
DP_ISPOLLED returns: 1
a.fd=0, a.events=34, a.revents=1
You can take any number instead of '34' and it will simply remain untouched
after the DP_ISPOLLED ioctl-request.
I hope it's clear now that the solaris8 and solaris9 (and probably solaris7
with /dev/poll patch too) DP_ISPOLLED implementation is broken.
This bug is also easily illustrated by looking at the solaris8 kernel sourcecode:
<snippet osnet_volume/usr/src/uts/common/io/devpoll.c:dpioctl()>
case DP_ISPOLLED:
pollfd_t pollfd;
polldat_t *pdp;
if (pollfd.fd < 0) {
mutex_exit(&pcp->pc_lock);
break;
pdp = pcache_lookup_fd(pcp, pollfd.fd);
if ((pdp != NULL) && (pdp->pd_fd == pollfd.fd) &&
(pdp->pd_fp != NULL)) {
pollfd.revents = pdp->pd_events;
if (copyout(&pollfd, (caddr_t)arg,
sizeof(pollfd_t))) {
mutex_exit(&pcp->pc_lock);
DP_REFRELE(dpep);
return (set_errno(EFAULT));
*rvalp = 1;
</snippet>
its' clearly visible that the code writes the current monitored events to
the revents field:
'pollfd.revents = pdp->pd_events;'
and that it doesnt set revents to zero.
It's funny to see that this has been like this since Solaris8 (possibly 7). That means nobody ever used DP_ISPOLLED that way or people were simply to lazy to file a bug report.
Another funny thing related to this. is that Hewlett-Packard did seem to know about this. Since HP-UX11i version 1.6 they also support /dev/poll. From their manual page i ll quote some sentences from their WARNING session:
"The ioctl(DP_ISPOLLED) system call also returns its result in the revents member of the pollfd structure, in order to be compatible with the implementation of the /dev/poll driver by some other vendors."
Hopefully this will get fixed.
I also like to reexpress my very negative feelings towards the fact that you're not able to file bug reports when you do not have a support contract. Ridiculous.
Thanks,
bighawk

Have I mentioned how much i love my playbook now Great job on os 2.0

The new Synaptics UltraNav: a few workarounds and minor bug report.

I only wanted to file bug report, but then decided to also share what I did with my touchpad configuration to make it more convenient for me. I have Thinkpad T540p so this might work differently or not work at all for other notebooks.
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If you didn't find some option, start regedit (using Win+R) and navigate to
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Set whatever option you want for 3-finger press. Then go to regedit and copy value from 3FingerPressButtonAction key to 3FingerTapAction.
#3 Button sizes and locations
You can change button bounds with keys like LeftButtonZoneX where X is L for left, R for right, T for top and B for bottom bounds. 0xFFFFFFFF ultimately means "unlimited in that direction". For finding other values defaults might be helpful. Trackpoint buttons keys are SlaveSomeButtonZoneX.
What for?
First, trackpoint buttons can cover the whole trackpad only when trackpad itself is disabled. By changing button sizes manually you can overcome this restriction. It is useful because trackpad does not respond well to pressing corners and when buttons cover it all you can press it somewhere in the middle.
Second, the same corner pressing problem exists for normal trackpad buttons so it is more convenient to use multi-finger taps or clicks. You can still hold trackpad pressed with one finger and use yet another finger to move mouse pointer.
At the same time when you tap or press with multiple fingers and one of them touches one of the buttons you get that button pressed instead of whatever you intended. It frustrated me a lot when I got context menu popups while trying to close chrome tabs with middle mouse button click. The solution is to set top bounds for left and right buttons to zero.
BUG (With the latest UltraNav drivers from support page)
When the middle trackpoint button (used for scrolling) is enabled, it is always enabled, no matter if you are using trackpont or touchpad. Left and right trackpoint buttons are properly disabled when you don't need them.
Even if you disable trackpoint completely without disabling that middle button first, it will remain enabled and will do nothing. (Blocking single- and multi-finger presses that touch it.)
I could not find a way to fix that problem with regedit.

Any problem can get official response and follow-up through a SR on Metalink/MOS (if you have a DB support contract), else you can post here and hope someone from development picks it up.
Regards,
K.

How do I file Bug Report? Labview FPGA

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