How to do video streaming in netgroup?

Hai ,
I did a sample code of netgroup and got text chat.I want to enhance it with video & audio streaming? i did the code for video streaming in separate functions. I called these functions in buttons.But i'm not able to start to video stream.I don't know hot put the video streaming code into netgroup.can anyone tell me?Also,if i'm keeping 2 display,how is it possible to switch the video streams wnen any peer want to communicate if there are more than 3 peers.One display must be the client's video and the other must be the requested peer's.
Ad.thanx

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#define WIDTH 320
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int ival;
T oval;
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converter.ival = e.data;
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volatile ap_uint<sizeof(T)> keep = e.keep;
volatile ap_uint<U> user = e.user;
volatile ap_uint<1> last = e.last;
volatile ap_uint<TI> id = e.id;
volatile ap_uint<TD> dest = e.dest;
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template<typename T, int U, int TI, int TD>
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int oval;
T ival;
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I also tried to delete or modify the following 2 lines in the modified IP core. But the transmitting problem existed too. It seems that the IP core cannot work normally if the receiving block and the transmitting block in different "for" loops. But if I did not solve this problem, the image processing functions cannot be added into the IP core either. The document of xapp1167 mentioned that " the hls::Mat<> datatype used to model images is internally defined as a stream of pixels". Does that caused the problem? And how can I solve this problem? Thanks a lot !
hls::Resize(mframe, mframe_resize);
hls::Resize(mframe_resize, mframe);

Hello
So the major concept that you need to learn/remember is that hls::Mat<> is basically "only" an hls stream -- hls::stream<> -- It's actually an array of N channels (and you have N=1).
Next, streams are fifos; in software that's modeled as infinite queues but in HW they have finite size.
The default value is a depth of 2 (IIRC)
in your first code you do :
for all pixels loop {
.. something to read pixel_in
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} // end loop
If you notice, mframe has never more than one pixel element inside since as soon as you write to it, you unload it. in other terms mframe never contains a full frame of pixel (but a full frame flow through it!).
In your second coding, mframe has to actually contain all the pixels as you have 2 for loops and you don't start unloading the pixels unless you have the first loop complete.
Needless to say that your fifo had a depth of 2 so actually you never read more than 3 pixels in.
That's why you see that the ready signal of the iput stream drops after a few pixels; that's the back pressure being applied by the VHLS block.
Where to go from there?
Well first stop doing FPGA tests and chipscope if you did not run cosim first and that it passed.
you would have done cosim and it had failed - or got stuck - then you would have debugged there, rather than waiting for a bitstream to implement.
Check UG902 about cosim and self checking testbench. maybe for video you can't have selfchecking so at least you need to have visual checks of generated pictures - you can adapt XAPP1167 for that.
For your design, you could increased the depth of the stream - the XAPP1167 explains that, but here it's impractical or sometimes impossible to buffer a full size frame.
If you check carefully the XAPP, the design operates in "dataflow" mode; check UG902 as to what this means.
In short, dataflow means that the HW functions will operate in parallel, and here the second loop will start executing as soon as data has been generated in the first loop - if you understand, the links between the loops is a stream / fifo, so as soon as a data is generated in the first loop, the second loop could process that; this is possible because the processing happens in sequential order.
Well I leave you to read more.
I hope this helps....

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