How to install counter pallets for PCI 6602 in labview 6.1

Hi...
Plz help me to install counter pallets and driver for PCI 6602

Hi...
Plz help me to install counter pallets and driver for PCI 6602

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  • DMA transfer rate for PCI-6602 counter/timer

    I'm strongly interested in raising the DMA transfer rate between the PCI-6602 counter and computer. At the moment, I've got a Pen-4 2.4GHz operating under Win98. I have to move an 80 Megaword array at an ~5 MHz speed. So far, I've been able to reach just 2 MHz. Would it be possible? What is the battleneck here - the soft- or hardware?

    Hello,
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  • Frequency divide by N doesn't work on Counter-Ti​mer PCI-6602

    Hello everybody,
    I tried to do something basic ( ?) with this Counter-Timer 6602 Board, and it doesn’t work.
    So I hope some people with more experience than me could understand what happens here.
    1) What I need:
    I need to generate 4 synchonised clocks, whose periods will be multiple of 1 ms.
    2) What I have:
    LabVIEW 7.0 and a PCI-6602 Counter-Timer Board in a DELL PC running under XP pro.
    The PCI-6602 Counter-Timer Board has 8 counter timers named CTR 0, CTR 1, ... CTR7.
    3) What I have already done, and that worked:
    - Generate a 1 kHz “Master Clock” signal from CTR 4, configured by “Continuous Pulse Generator Config.vi” (found in “Data Acquisition, Counters...).
    - configure CTR 0 and CTR 1 to work as frequency dividers, by use of “Down Counter or Divider Config.vi”.
    - Apply the output signal of CTR 4 (OUT ) to the SOURCE inputs of CTR 0 and CTR 1 by means of physical wiring in the SCB-68 connection box.
    When I do this, I get two nice secondary clock signals on my oscilloscope screen, ( with periods = 3 ms, or 5 ms or whatever multiples of 1 ms I choose) from CTR 0 and CTR 1 outputs , very clean and perfectly in phase with the 1 kHz Master Clock.
    So far, so good...
    But I still need 2 more secondary clocks...
    One would say: “No problem, do the same trick with two other counters...” Well, not so simple, it seems...
    4) What I tried to do, and that didn’t work:
    When I try to do the same frequency division with any of the remaining counters, (CTR2 to CTR7), the program stops and I get an error “ –10020 : Time base not valid “.
    I can’t figure out what happens here: I thought any counter could be configured to work as a frequency divider, but it seems not to be so, and I am stuck here.
    Has anyone an idea about how to fix this type of problem?
    Attached file: hor_div02New.vi
    Attachments:
    hor_div02New.vi ‏123 KB

    karolik,
    I'm just adding a followup in English. As Marc L. mentioned, the particular vi named "Down Counter or Divider Config" isn't compatible with the 6602. While the 6602 does have the ability to generate 4 synchronized clocks, a different syntax is needed. Here's how I'd do it:
    Traditional NI-DAQ
    1. Configure a continuous pulsetrain on CTR 4. Route its output to, say, RTSI 4. Don't start it yet.
    2. Configure CTR 0,1,2,3 for continuous pulsetrains using RTSI 4 as their "timebase source." Start them.
    3. Start the CTR 4 pulsetrain.
    4. Now CTR's 0-3 should generate separate clocks with synchronized phasing.
    DAQmx
    1. Configure a continuous pulsetrain on CTR 4. Don't start it yet.
    2. Configure CTR 0,1,2,3 for continuous pulsetrains using "Ticks" for units. Use a DAQmx property node (probably Channel property node, but am not 100% sure and don't have a LV PC handy to check) to specify that the "ctr4 internal output" should be used as the timebase. Start them.
    3. Start the CTR 4 pulsetrain.
    4. Now CTR's 0-3 should generate separate clocks with synchronized phasing.
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