How to let Signal 2 rise only when Signal 1 is High with 2us delay

I am using PCI-6229 DAQ card.
1) I want to generate a signal 2. It change from low to high. I want the rising edge only happens at the area where Signal 1 is high.
Also, the rising edge of signal 2 must heppens 2us or more later than the moment Signal 1 rise.
Signal 1 is a 20H Hz, 30% duty cycle digital signal. I use P0.0 to generate this signal.
2) Similar to 1). The difference is Signal 1 is a digital input channel. Also 20K Hz, 30% duty cycle.
Thanks

Hi James McN,
Thanks James. I write the VI following you suggestion, which is in the file attached.Gen Dig Pulse Train-Continuous-Dig Start_Counter_2.vi
I think I may not descibe my question clear enough. So I draw the instruction. You can find it the file attached: Des.doc.
But still have problem. It seems the delay time doesn't work.
Could you help me to modify my VI? Also, I have another question. Is it possible to use digital output channel to work as signal 2, rather than a counter?
thanks
Ossoo
Attachments:
Des.doc ‏31 KB
Gen Dig Pulse Train-Continuous-Dig Start_Counter_2.vi ‏24 KB

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