How to reorder user XDC file with respect to IP XDC?

Hi All, 
How do i  set a user XDC files to be processed affter all other xdc files(specially those *_clocks.xdc from IP)?Figure attached show the snapshot of my project from the command "report_compile_order -constraints". 
i would like to have the tri_mode_ethernet_mac_0_user_phytiming.xdc to be processed last among the rest. This reason is for me to overwrite the xdc constraints values provided with the MAC IP core. 
i have the set the processing order of this xdc file to the late and also tried the "reorder_files" command, but nothing seems work.
advanced thanks for your help. 
 

Hi ,
I achived my goal of having the IP XDC files that i want to processed before the user_phytiming.xdc. This done by having the PROCESSING_ORDER of IP XDC files set normal. 
just for sharring, all this while i been focusing on manipulating the  PROCESSING_ORDER user_phytiming.xdc instead of the IP XDC files. 
The log of "report_compile_order -constraints" is shown below.
Now, tri_mode_ethernet_mac_0_user_phytiming.xdc is processed after the tri_mode_ethernet_mac_0_clocks.xdc(IP XDC) which enable me to overwire the IP constraints to suit my system.
report_compile_order -constraints
INFO: [Vivado 12-3442] The output from report_compile_order is primarily targeted for human readability and ease of use. As such, the format and details in the output below could change over time. The 'get_files -compile_order' command produces this same information, but in a format that is better suited for using in any automated scripts, and is less likely to change format over time.
Constraint evaluation order for 'synthesis' with fileset 'sources_1' & with fileset 'constrs_1':
Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context
1 iCAKM_EDGE_ARTIX7.xdc Synth & Impl NORMAL
2 tri_mode_ethernet_mac_0_user_phytiming.xdc Synth & Impl LATE
Constraint evaluation order for 'implementation' with fileset 'sources_1' & with fileset 'constrs_1':
Index File Name Used_In Scoped_To_Ref Scoped_To_Cells Processing_Order Out_Of_Context
1 tri_mode_ethernet_mac_0_board.xdc Synth & Impl tri_mode_ethernet_mac_0 U0 EARLY
2 tri_mode_ethernet_mac_0.xdc Synth & Impl tri_mode_ethernet_mac_0 U0 EARLY
3 afifo_CbCr2JPEGENC.xdc Synth & Impl afifo_CbCr2JPEGENC U0 EARLY
4 afifo_data.xdc Synth & Impl afifo_data U0 EARLY
5 afifo_data_buffer.xdc Synth & Impl afifo_data_buffer U0 EARLY
6 afifo_length.xdc Synth & Impl afifo_length U0 EARLY
7 afifo_OV2715_BUF.xdc Synth & Impl afifo_OV2715_BUF U0 EARLY
8 afifo_pkt_length_buffer.xdc Synth & Impl afifo_pkt_length_buffer U0 EARLY
9 afifo_sync.xdc Synth & Impl afifo_sync U0 EARLY
10 afifo_y2jpegenc.xdc Synth & Impl afifo_y2jpegenc U0 EARLY
11 iCAKM_EDGE_ARTIX7.xdc Synth & Impl NORMAL
12 tri_mode_ethernet_mac_0_clocks.xdc Synth & Impl tri_mode_ethernet_mac_0 U0 NORMAL
13 tri_mode_ethernet_mac_0_user_phytiming.xdc Synth & Impl LATE
14 afifo_CbCr2JPEGENC_clocks.xdc Synth & Impl afifo_CbCr2JPEGENC U0 LATE
15 afifo_data_buffer_clocks.xdc Synth & Impl afifo_data_buffer U0 LATE
16 afifo_OV2715_BUF_clocks.xdc Synth & Impl afifo_OV2715_BUF U0 LATE
17 afifo_pkt_length_buffer_clocks.xdc Synth & Impl afifo_pkt_length_buffer U0 LATE
18 afifo_sync_clocks.xdc Synth & Impl afifo_sync U0 LATE
19 afifo_y2jpegenc_clocks.xdc Synth & Impl afifo_y2jpegenc U0 LATE
20 v_ccm_0_clocks.xdc Synth & Impl v_ccm_0 U0 LATE
21 v_cfa_0_clocks.xdc Synth & Impl v_cfa_0 U0 LATE
22 v_enhance_0_clocks.xdc Synth & Impl v_enhance_0 U0 LATE
23 v_gamma_0_clocks.xdc Synth & Impl v_gamma_0 U0 LATE
24 v_rgb2ycrcb_0_clocks.xdc Synth & Impl v_rgb2ycrcb_0 U0 LATE
25 v_vid_in_axi4s_0_clocks.xdc Synth & Impl v_vid_in_axi4s_0 inst LATE
Thanks you very very much. Have a nice day :-)
 

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