How to take the floating point adder output

I have a piece of code in VHDL here : Floating Point(IP Core) Adder.
I want to take the result_fp to the output signal test. The result_fp is not affecting the test signal.
Line 142 :  test <= STD_LOGIC_VECTOR(b_fp);
I have tried with
test <= STD_LOGIC_VECTOR(result_fp);
as well as
test <= result_fp;
Not working.
How can I solve this.
clockIn input is fed with a square wave of 50 ns period.
clk_fp is fed with a square wave of 10 ns period(faster clock).
Timing diagram:

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