IDOC Sender Partner has changed after transporting Integration Directory ob

Greetings,
After we did a transport from QA to PR for a new interface (Intergration Directory) objects were transported,
The sender partner has changed to QA in all outbound IDOCs generated in XI PR.
I checked the adapter-specific identifiers and it is showing as production.
Any hint where I should check?

Found it in the filesystem communication channel as QA and changed it to PR

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Unable to convert partner to IDoc sender partner

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Vishal,
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Idoc will be processed in SAP ECC based on the sender details (snprn,sndpor,sndpfc...) of idoc control record..
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Thanks a lot for replies, but i have tried all these options but no luck. Does it need any additional configurtion to resolve this issue, i dont think this is cache issue, if that is the case after all steps which i have done should have fixed it. Please post your comments.
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Message was edited by: Srujan Gogineni

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>>>>How can I assign Service Without Party / Business System Service to point to interfaces that require new SWCV?
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I explain the situation I´m experimenting right now:
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Thanks Barry
That menu option is available to me too but there is no option to use CTS+ in the pull down list.
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Dear experts,
I am currently working on a digital triangular shaping using the 7966R FPGA + 5734 AI. I am using LabView 2012 SP1.
Some days ago I have encountered a problem with my FIFOs that I have not been able to solve since. I'd be glad if somebody could point out a solution/ my error.
Short description:
I am writing U16 variables between ~32700-32800 to a U16 configured FIFO. The FIFO output does not coincide with the data I have been writing to the FIFO but is rather bit-shifted or something is added. This problem does not occure if I execute the VI on the dev. PC with simulated input.
What I have done so far:
I am reading all 4 channels of the 5734 inside a SCTL. The data is stored in 4 feedback nodes I am applying a triangular shaping to channel 0 and 1 by using 4 FIFOs that have been prefilled with a predefined number of zeros to serve as buffers. So it's something like (FB = Feedback node):
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This code shows NO weird behaviour and works as expected.
The Problem:
To reduce the amount of FIFOs needed I then decided to interleave the data and to use only 2 FIFOs instead of 4. You can see the code in the attachment. As you can see I have not really changed anything to the code structure in general.
The input to the FIFO is a U16. All FIFOs are configured to store U16 data.
The data that I am writing to the FIFO can be seen in channel 0 of the output attachment.
The output after passing through the two FIFOs can be seen in channel 2 of the same picture.
The output after passing through the first FIFO (times 2) can be seen in channel 3 of the picture.
It looks like the output is bit-shifted and truncated as it enters Buffer 1. Yet the difference between the input and output is not exactly a factor of 2. I also considered the possibility that the FIFO adds both write operations (CH0 + CH1) but that also does not account for the value of the output.
The FIFOs are all operating normally, i.e. none throws a timeout. I also tried several different orders of reading/writing to the FIFOs and different ways of ensuring this order (i.e. case strucutres, flat and stacked sequence). The FIFOs are also large enough to store the amount of data buffered no matter if I write or read first.
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Attachments:
FPGA-code.png ‏61 KB
FPGA-output.png ‏45 KB

During the last couple of days I tried the following:
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2. I tested the code on the development PC with the square and sine wave generation VI as 'simulated' I/O. The code performed normal.
3. I replaced the FIFOs with queues and ran my logic on the dev. PC. The logic performed totally normal.
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I am currently trying to get LabView 2013 on the development machine. It seems like my last real hope is that the issue is a bug in the XILINX 13.4 compiler tools and that the 14.4 tools will just make it disappear...
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Buffer 1 and 2:
- Type: Target Scoped
- Elements Requested: 1023
- Implementation: Block Memory
- Control Logic: Target Optimal
- Data Type: U16
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- No. Elements Per Read: 1
- Arbitrate for Write: Never Arbitrate
- No. Elements Per Write: 1
The inputs from the NI 5734 are U16 so I am wirering the right data type to the FIFOs. I also don't have any coercion dots within my FPGA VI. And so far it has only occured after the VI has been compiled onto the FPGA. Could some of the FIFOs/block memory be corrupted because we have written stuff onto the FPGA too often?

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IDOC Sender Partner has changed after transporting Integration Directory ob

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