Implementation IP-cores turn into black boxes

Question

Hi,
I want to learn about FPGA programming, thus I got a ZedBoard.
I use Mult-IP-Cores from the IP Catalog.
After I run the "Generate Output Products" and synthesis I want to run implementation.
But I get an error:
"While importing the netlist, 2 undefined cells were found and coverted to black boxes.
Make sure you have loaded all intended module definitions before proceeding.
Black boxes can be populated by using the Add Sources operation and re-running Synthesis.
Module names: mult_gen_v12_0, mult_gen_v12_0_parameterized1"
When I use the bitstream for my ZedBoard, it obviously doesn't work properly.
I'm using Vivado 2015.1.
Thanks for help and greeting from Poland!

Answer 1

Hi,
Can you try 'reset output products' then 'generate output products' for the "mult_signed" and let us know the results.
Also share the generated synthesis log.
Thanks,
Anusheel
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