IMPORTANT T- codes in excise .
Hi can any one give me important t-codes in various Excise related Business Transactions?( including various RG registers updated)
Regards,
Deepika
Hi Deepeka,
Please find here the Main CIN transactions with descriptions
J1I2 Prepare a sales tax register
J1I3 Create outgoing excise invoices in batches
J1I5 Update the RG 1 and Part I registers
J1I8 Post the challan used to remit TDS
J1IC194C Create annual return under section 194 C (Classic TDS)
J1IC194D Create annual return under section 194 D (Classic TDS)
J1IC194I Create annual return under section 194 I (Classic TDS)
J1IC194J Create annual return under section 194 J (Classic TDS)
J1IEX Incoming Excise Invoices (central transaction)
J1IEX_C Capture an incoming excise invoice (excise clerk)
J1IEX_P Post an incoming excise invoice (excise supervisor)
J1INBANK Post a bank challan
J1INCANC Cancel a vendor withholding tax certificate
J1INCERT Print a vendor withholding tax certificate
J1INCHLN Create a remittance challan
J1INCUST Post a customer withholding tax certificate
J1INHC Withholding Tax Migration Health Check Program
J1INMIG Withholding Tax Data Migration Tool
JI1NCHLC Create a remittance challan for customers
J1INCC Print customer withholding tax certificates
J1INMIS Withholding Tax Information System
JI1NAR Prepare annual returns (Extended Withholding Tax)
J1IF01 Create a subcontracting challan
J1IF11 Change a subcontracting challan
J1IF12 Display a subcontracting challan
J1IF13 Complete, reverse, or recredit a subcontracting challan
J1IFQ Reconcile quantities for subcontracting challans
J1IFR List subcontracting challans
J1IH Make a CENVAT adjustment posting
J1IIN Create an outgoing excise invoice
J1IJ Assign excise invoices to a delivery for sales from depots
J1INJV Adjust withholding tax Item
J1INREP Reprint a vendor withholding tax certificate
J1INREV Reverse a remittance challan
J1INPR Calculate withholding tax on clearing accounts
J1INUT Clear withholding tax on clearing accounts
J1IR Download register data
J1IS Process an excise invoice (outgoing) for other movements
J1IU Process exemption forms
J1IW Verify and post an incoming excise invoice
J1IX Create an incoming excise invoice (without reference to purchase order)
J2I8 Transfer excise duty to CENVAT account
J2ID Archive tax deducted at source (TDS) documents
J2IE Locate tax deducted at source documents in archive
J2IU Remit excise duty fortnightly
J2I9 Monthly CENVAT return
J1IG Excise invoice entry at depot
J1IGA Create additional excise entry at depot
J2I5 Extract data for excise registers
J2I6 Print excise registers
rgds
Chidanand
Similar Messages
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JAEHYLEE (R11i AP) Payables Open Interface Import REJECT CODE:NO TERMS
Purpose
Payables Open Interface Import REJECT CODE:NO TERMS
Symptoms
'EDI' Source로 invoice를 import할때 Payables Open Interface Import program 이 error로 종료된다
정상적인 에러 No Terms로 출력이 되나 , 데이타 상에는 아무 이상이 없으며
debug log file 의 reject code는 NO TERMS INFO라고 출력된다
REJECT CODE:NO TERMS INFO
CauseThe import program in procedure v_check_invalid_terms does not have exception handling. So, when ever it has exceptions like no_data_found or too_many_rows control was returning to the final exception block and the procedure was returning false to the calling procedure. Hence the error instead of Reject reason.
Bug 4704918 - APXIIMPT DOESN'T REJECT INVOICES WITH INCONSISTENT TERMS.
Solution
AP.N이상에서 patch 4755024를 적용
Please apply Patch 4755024 - 1OFF:4704918:AP.N:FP.G:11.5.10:APXIIMPT DOESN'T REJECT INVOICES
Reference
Note 359089.1Have you customized/setup the Project Accounting Workflow builder. You need to do some setup for this workflow builder so that the project accounts can be derived properly.
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T.code for excise register closing
Hi All,
What are the T code for excise register closing. can any one tell me the step by step closing T code in sap.
thanks in advance
points will be given.Dear Gopi,
You can use the transaction SM30, table V_T001B or by SPRO Financial Accounting -> Financial Accounting Global Settings -> Document -> Posting Periods -> Open and Close Posting Periods.
Also, check the transaction F.16.
Thanks and regards,
Paulo eVARISTO -
What are the importent transaction codes in edi
what are the importent transaction codes in edi
hi,
=>sale - ALE Customizing
=>bale - Distribution Administration (ALE)
=>wedi - IDOC Type and EDI Basis
=>shdb - BDC (Transaction Recorder)
=>lsmw - LSMW
=>bapi - BAPI
=>spau - Display Modified DE Objects
=>spdd - Display Modified DDIC Objects
=>sara - central idoc archiving
=>stms - Transport Management System
=>wedi - IDOC Type and EDI Basis (IDOC Configuration)
=>bd21 - Analyze change pointers - create IDOC from change pointer
=>bd10 - Send Material Master
=>bd12 - Send Customer Master
=>bd14 - Send Vendor Master
=>bd50 - Activate Change Pointer for Message Type
=>bd55 - Conversion rule user exit (Link conversion rule user exit to the different system \ partner combinations)
=>bd54 - Maintain Logical Systems
=>bd71 - Distribute Customer Model
=>bd87 - Process Inbound IDOCs
=>bd88 - Process Outbound IDOCs
=>bdm2 - Cross-system IDOC Reporting
=>bdm7 - ALE Audit - statistical analyses
=>bdm8 - ALE Audit - sending confirmations
=>bd61 - Activate Change Pointer generally
=>bmv0 - Direct Input Data Transfer Administration
=>rz04 - Operation Mode
=>rz12 - RFC Server Group Maintenance
=>sar3 - Archiving object customizing
=>s001 - SAPoffice Inbox
=>s010 - Standards Texts (SAP Script)
=>se01 - Transport Organizer (Extended View - Performing and managing the transport of development object across different systems)
=>se09 - Transport (Workbench) Organizer (Controlling and keeping track of Development work and Development Objects)
=>se78 - Administration of Form Graphics (Import Graphics into SAP System)
=>se84 - ABAP Repository Information (search for SAP objects)
=>su01 - User Maintenance (Security)
=>su02 - Maintain Authorization Profiles
=>su03 - Maintain Authorizations
=>sm36 - Background Job Scheduling
=>sm37 - Background Job Monitoring (display batch jobs)
=>sm31 - Table Maintenance
=>sm30 - Calling View Maintenance
=>sm35 - Batch Input Monitoring (Error Logs)
=>sm50 - Process Overview
=>sm58 - Transactional RFC Monitoring
=>sm59 - Maintain RFC Destinations (Define RFC Configuration)
=>snro - Number Range Objects (for IDOCs)
=>we02 - Display IDOC
=>we05 - IDOC lists
=>we07 - IDOC statistics
=>we12 - Inbound processing of outbound file - convert outbound to inbound file
=>we14 - Process (dispatch) IDOCs through Port - RSEOUT00
=>we15 - Outbound IDOC from NAST - message control
=>we16 - Inbound File
=>we18 - Generate status file
=>we19 - Test tool
=>we20 - Add new Message Type to Partner Profile
=>we21 - Maintain Port Definition
=>we30 - IDOC Type development
=>we31 - IDOC Segment development
=>we41 - Process Code Outbound
=>we42 - Process Code Inbound
=>we46 - IDoc Administration
=>we47 - Status Code Maintenance
=>we57 - Assign function module to logical message and IDoc type
=>we63 - IDOC Type for Parser Output
=>we82 - Assign IDOC to Message Type
=>we60 - IDOC Documentation - IDOC Types
=>we61 - IDOC Documentation - IDOC Record Types
=>we81 - Create new IDOC Message Types
=>we82 - Assign IDOC to Message Type
=>pa20 - Display HR Master Data
=>pa30 - Maintain HR Master Data
=>bd59 - Create and assign Filter Object Type for Message Type
=>bd64 - Maintenance of ALE or any other Distribution Model
Hope this helps, Do reward. -
How to import Verilog codes into LabVIEW FPGA?
I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip 57 KBHi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
input in1,in2;
output reg out1;
always@( in1 or in2)
begin
out1 <= in1 & in2;
end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
port (
in1 : in std_logic;
in2 : in std_logic;
out1 : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
port(
in1 : in std_logic;
in2 : in std_logic;
out1 : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
port map(
in1 => in1,
in2 => in2,
out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd" Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type 'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt 256 KB
labview project files.zip 51 KB -
How to import activity codes into P6 from Excel sheet?
Please refer to 200326112033 in our knowledgebase for
more information on how to import and export activity
codes from excel. If you have any further questions
please contact support at
http://primavera.com/customer/support.asp. <br
/>
Saryn -
Error at the Time of Importing Tax Codes
Hi All
I m in the process of importing Tax Codes into the Production Environment; However, everytime i import the Transport Number, I get the below Error:
Tax jurisdiction CA1023000001 has defective structure
Message no. FS790
The Tax Jurisdiction has already been set up in OBCP...
Has anyone enocountered this before...
Thank u
RukshanaHi Rukshana,
I haven't encountered this error before, but Jurisdiction Code "CA1023000001" seems incorrect.
If it is a US Jurisdiction Code, the length should be 10 (2 + 3 + 4 + 1); and if it is Canadian Jurisdiction Code, the length should be 4 (2 + 2).
Check where this code definition is coming from and you will be able to isolate the problem.
HTH,
Manish Patel
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In PO I have checked the import tab in the header level. but unable to find out field as commodity code/import data.
I have already maitained the code to material master.
to where can I find the field commodity code in PO in import tab of the po.
or is it required any addition setting.
pls let me know .hi dear,
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thanks
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where do you get this file in .tsv format from?
I guess from a data provider?
First thing I would do is to ask the data provider to send the file in another GTS compatible format.
If you have no influence on the file format which is beeing delivered to you I would just convert those files.
Easiest tool to convert those files with might be Excel since almost everyone is using it.
You can import the .tsv into excel and save it as a .xml file afterwards.
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} I want to import this code into my form in order to execute it.
Code make possible drawing graphs to screen...
What I want is to execute this code into my form, in a when-new-block instance trigger or something else.
How can I achieve this???
Thanks all for collaboration,
FabrizioIt isn't quite as simple as just "importing" your java code if your goal is to have the forms and the java app communicate with each other. Interaction occurs when a properly designed Java Bean is created.
Take a look at some of the examples on the following page as they can likely provide you with a good starting place:
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Hai...
Can any one tell where to enter import export code in SAPHi,
In Material Master Foreign Trade Import and Foreign Trade export we have to maintain either HS code or IEC number depending on the requirement.
Regards,
Sharan -
Hi Guru,
Can anyone give important T-codes in WM? i am new to WM?
regards,
prabakaranHi,
T codes
LCO1 Set Up Warehouse Co/Material Docs.
LCO2 Set Up Warehouse Co/Transport Orders
LL01 Warehouse Activity Monitor
LS01 Create Warehouse Master Record
LS01N Create Warehouse Master Record
LS02 Change Warehouse Master Record
LS02N Change Warehouse Master Record
LS03 Display Warehouse Master Record
LS03N Display Warehouse Master Record
LS26 Warehouse stocks per material
MB52 List of Warehouse Stocks on Hand
OLML IMG structure Warehouse Management
OMLN Warehouse Control Link
OMMF Number Ranges per Warehouse
OMMP Decentralized Warehouse Management
OMNG Queues Warehouse Management System
OMNH APPC Interface per Warehouse Number
OMNI Print Program per Warehouse Number
OMNJ Link to Warehouse Control Unit
OMNL Warehouse Number Maint./Inventory
EC09 Org.Object Copier: Warehouse Number
FMFG_WAREHOUSE Warehouse Report Transaction
J1A5 MM Warehouse stock report (Arg.)
LI20 Clear Inventory Differences WM
LLVS WM Menu
LN07 Number Ranges for WM Communic.Rec.
LP11 WM staging of crate parts
LP11W WM Staging for Crate Parts (IAC)
LP12 Staging release order parts (WM-PP)
LP21 WM replenishment for fixed bins
LP24 WM Replenishment for Random Whse
LPIN Info: Material Stock WM-PP
LPK1 Create Control Cycle for WM
LPK2 Change Control Cycle for WM
LPK3 Display Control Cycle for WM
LS51 Create Batch Search Strategy - WM
LS52 Change Batch Search Strategie - WM
LS53 Display Batch Search Strategy - WM
LX23 Stock comparison IM - WM
LX26 Inventory in WM via cycle counting
LX30 Overview of WM messages ext.system
LX41 Bin Status Report WM/PP Interface
LX42 Evaluation PP Order from WM View
LX46 Transmission WM perform. data to HR
MCL1 WMS: Stck Placemt.+Remov. Selection
MCL5 WMS: Flow of Quantities Selection
MCL9 WM: Material Plcmt/Removal:Selection
MCLD WM: Material Flow - Selection
MCLH WM: Movement Types - Selection
OMCR Inventory Sampling: St.Mgmt Lvl: WM
OMK3 Conditions: field catalog (WM)
OMK4 CondTable: Create (Batches, WM)
OMK5 CondTable: Change (Batches, WM)
MCL1 WMS: Stck Placemt.+Remov. Selection
MCL5 WMS: Flow of Quantities Selection
MCL9 WM: Material Plcmt/Removal:Selection
MCLD WM: Material Flow - Selection
MCLH WM: Movement Types - Selection
OMCR Inventory Sampling: St.Mgmt Lvl: WM
OMK3 Conditions: field catalog (WM)
OMK4 CondTable: Create (Batches, WM)
OMK5 CondTable: Change (Batches, WM)
OMK6 CondTable: Display (Batches, WM)
OMK7 Batch WM..... (will be deleted)
OMKR Search Types: Optimize Access WM
OMKT Strategy Types: Batch Determin.WM
OMKU Access: Maintain Batch Determin.WM
OMKV Batch Determination: Proced.for WM
OMLL WM Movement Type: Clear Invent.Diff.
OMLR WM Interface to Inventory Management
OMMC Printer Assignment per WM Mov.Type
OMMO Consistency Check for MM-WM Tables
OMMZ Spool Parameters for WM Print Ctrl
OMN0 Control of Transaction Codes (MM-WM)
OMNE Control of Transactions in MM-WM
OMNZ Parameters for Activity in WM
Warehouse management - Configuration Guide:
http://help.sap.com/bestpractices/BBLibrary/documentation/Q03_BB_ConfigGuide_EN_IN.doc#_Toc77662927 -
Is it possible to import Tracking Codes with Cisco WebEx Meetings Server 2.5?
Is it possible to import Tracking Codes with Cisco WebEx Meetings Server 2.5?
Hi,
In documentation, you can find only what is possible and supported in the product. We don't document what is not supported.
At this time, there is no feature request submitted for this as I assume no one requested such a feature. If your customer really needs this feature, I advise you to reach out to your/their Cisco Account Manager, explain the feature you would like to see, so they can reach out to Product Management and see if this could be built in the next product version.
I hope this helps.
-Dejan -
TEMPLATE FOR IMPORTING SEQUENCE CODE TO SAP B1
Dear Experts
is there any template(dtw) available for importing sequence code to sap b1.
thanksHi,
This function is only available to few localizations like India. It is therefore not available to DI API. There is no template for DTW it.
Thanks,
Gordon -
Important T-codes of SD module
Dear Friends,
Can anyone get me important t-codes of SAP SD Module<u><b>Sales Order Management Transactions</b></u>
<u>SALES ORDER PROCESSING</u>
Creating Sales Order - <b>VA01</b>
Maintaining a Sales Order - <b>VA02</b>
Displaying a Sales Order - <b>VA03</b>
Releasing an Order or Delivery from Credit Hold: Non-Flooring - <b>VKM1</b>
Display List of RMAs by Customer - <b>VA05</b>
Confirm RMA Goods Receipt - <b>VL02</b>
Generate list of open return orders for deletion - <b>VA05</b>
Display Customer returns eligibility - <b>MCSI</b>
Removing a Billing Block (Approving Credit/Debit Requests) - <b>V.23</b>
<u>PRICING MASTER DATA</u>
Create Pricing - <b>VK11</b>
Creating a Sales Deal - <b>VB21</b>
Maintaining a Sales Deal - <b>VB22</b>
Displaying a Sales Deal - <b>VB23</b>
Maintaining Prices - <b>VK12</b>
Displaying Prices - <b>VK13</b>
<u>MATERIAL MASTER DATA</u>
Creating Material Substitution Master Data - <b>VB11</b>
Maintaining/Deleting Material Substitution Master Data - <b>VB12</b>
Displaying Material Substitution Master Data - <b>VB13</b>
Creating a Bundled Master - <b>MM01</b>
Creating a Sales BOM - <b>CS01</b>
Maintaining a Sales BOM - <b>CS02</b>
Displaying a Sales BOM - <b>CS03</b>
<u>CUSTOMER MASTER DATA</u>
Creating Partner Records - <b>XD01</b>
Maintaining Customer Master Data - <b>XD02</b>
Displaying Customer Master Data - <b>XD03</b>
Deactivating a Partner - <b>VD06</b>
<u>CUSTOMER CREDIT INFO</u>
Creating/Maintaining New Customer Credit Information - <b>FD32</b>
Displaying Customer Credit Information - <b>FD33</b>
Blocking or Unblocking a Customer - <b>VD05</b>
<u>SHIPPING</u>
Creating a Delivery - <b>VL01N</b>
Displaying a Delivery - <b>VL03N</b>
Changing a Delivery - <b>VL02N</b>
Deliveries due - <b>VL06O</b>
Deliveries due for PGI - <b>VL06G</b>
Shipment Inquiry / Display - <b>VT03</b>
Adjusting Transfer Order - Confirmation Quantity - <b>LT12</b>
Collectively Confirm Transfer Order - <b>LT25</b>
Batch Shipment Confirmation - <b>VL19</b>
PGI Reversal Cancellation - <b>VL09</b>
Creating Service Provider/Carrier Master Data - <b>XK01</b>
Maintaining Serive Provider/Carrier Master Data - <b>XK02</b>
Displaying Service Provider/Carrier Master Data - <b>XK03</b>
Maintaining Product Master/Serial # Profile/Unit of Measure/Shipping Unit - <b>MM02</b>
IDoc Inquiry - <b>WE02 / WE05</b>
<u>BILLING</u>
Invoicing a Customer Shipment - <b>VF01</b>
Reprinting an Invoice - <b>VF31</b>
Releasing a Sales Order for Billing - <b>V.23</b>
Creating an Invoice by Using the Billing Due List - <b>VF04</b>
Checking Open Billing Documents - <b>VF05</b>
Create Credit/Debit Memo - <b>FB01</b>
<u>A/R</u>
Controlling Total Debit/Credit bkgs - <b>F.03</b>
Generate FI Account balance - <b>F.08</b>
Generate Month-to-date Inv. register - <b>F.02</b>
Process payments - <b>FBZ1</b>
Rqst Individual Customer Corresp. - <b>FB12</b>
Generate Customer Correspondence - <b>F.61</b>
Enter Batch totals under Control ttl - <b>FB07</b>
Display G/L Acct. totals - <b>FBL3N</b>
Reverse Posted Amounts - <b>FB08</b>
Customer Refunds - <b>FBL6</b>
Customer Refund to other than Payer - <b>FB05</b>
Clearing Debit/Credit on Cust. acct. - <b>FB1D</b>
Customer Balance in Local Currency - <b>F.23</b>
G/L Account Balance Report - <b>F.08</b>
Create Invoice - legal entity adjust - <b>FB01</b>
Generate Cust. Acct. statements - <b>F.27</b>
Generate Dunning Letters - <b>F150</b>
Generate Billing Due List - <b>VF04</b>
Generate Blocked Billing Doc list - <b>VFX3</b>
Inq. via Credit Release Screen - <b>VKM1</b>
List orders by partner - <b>VA05</b>
Past Due invoices by customer - <b>FD11</b>
Check number info by G/L account - <b>FBL3N</b>
Display customer Line items - <b>FBL5N</b>
Regards,
Rajesh Banka
Reward points if helpful.
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