Important T-codes of SD module

Dear Friends,
Can anyone get me important t-codes of SAP SD Module

Sales Order Management Transactions
SALES ORDER PROCESSING
Creating Sales Order - VA01
Maintaining a Sales Order - VA02
Displaying a Sales Order - VA03
Releasing an Order or Delivery from Credit Hold: Non-Flooring - VKM1
Display List of RMAs by Customer - VA05
Confirm RMA Goods Receipt - VL02
Generate list of open return orders for deletion - VA05
Display Customer returns eligibility - MCSI
Removing a Billing Block (Approving Credit/Debit Requests) - V.23
PRICING MASTER DATA
Create Pricing - VK11
Creating a Sales Deal - VB21
Maintaining a Sales Deal - VB22
Displaying a Sales Deal - VB23
Maintaining Prices - VK12
Displaying Prices - VK13
MATERIAL MASTER DATA
Creating Material Substitution Master Data - VB11
Maintaining/Deleting Material Substitution Master Data - VB12
Displaying Material Substitution Master Data - VB13
Creating a Bundled Master - MM01
Creating a Sales BOM - CS01
Maintaining a Sales BOM - CS02
Displaying a Sales BOM - CS03
CUSTOMER MASTER DATA
Creating Partner Records - XD01
Maintaining Customer Master Data - XD02
Displaying Customer Master Data - XD03
Deactivating a Partner - VD06
CUSTOMER CREDIT INFO
Creating/Maintaining New Customer Credit Information - FD32
Displaying Customer Credit Information - FD33
Blocking or Unblocking a Customer - VD05
SHIPPING
Creating a Delivery - VL01N
Displaying a Delivery - VL03N
Changing a Delivery - VL02N
Deliveries due - VL06O
Deliveries due for PGI - VL06G
Shipment Inquiry / Display - VT03
Adjusting Transfer Order - Confirmation Quantity - LT12
Collectively Confirm Transfer Order - LT25
Batch Shipment Confirmation - VL19
PGI Reversal Cancellation - VL09
Creating Service Provider/Carrier Master Data - XK01
Maintaining Serive Provider/Carrier Master Data - XK02
Displaying Service Provider/Carrier Master Data - XK03
Maintaining Product Master/Serial # Profile/Unit of Measure/Shipping Unit - MM02
IDoc Inquiry - WE02 / WE05
BILLING
Invoicing a Customer Shipment - VF01
Reprinting an Invoice - VF31
Releasing a Sales Order for Billing - V.23
Creating an Invoice by Using the Billing Due List - VF04
Checking Open Billing Documents - VF05
Create Credit/Debit Memo - FB01
A/R
Controlling Total Debit/Credit bkgs - F.03
Generate FI Account balance - F.08
Generate Month-to-date Inv. register - F.02
Process payments - FBZ1
Rqst Individual Customer Corresp. - FB12
Generate Customer Correspondence - F.61
Enter Batch totals under Control ttl - FB07
Display G/L Acct. totals - FBL3N
Reverse Posted Amounts - FB08
Customer Refunds - FBL6
Customer Refund to other than Payer - FB05
Clearing Debit/Credit on Cust. acct. - FB1D
Customer Balance in Local Currency - F.23
G/L Account Balance Report - F.08
Create Invoice - legal entity adjust - FB01
Generate Cust. Acct. statements - F.27
Generate Dunning Letters - F150
Generate Billing Due List - VF04
Generate Blocked Billing Doc list - VFX3
Inq. via Credit Release Screen - VKM1
List orders by partner - VA05
Past Due invoices by customer - FD11
Check number info by G/L account - FBL3N
Display customer Line items - FBL5N
Regards,
Rajesh Banka
Reward points if helpful.

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what are the importent transaction codes in edi

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How to import Verilog codes into LabVIEW FPGA?

I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip ‏57 KB

Hi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
 input in1,in2;
 output reg out1;
 always@( in1 or in2)
 begin
 out1 <= in1 & in2;
 end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
 port (
 in1 : in std_logic;
 in2 : in std_logic;
 out1 : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
 port(
 in1 : in std_logic;
 in2 : in std_logic;
 out1 : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
 port map(
 in1 => in1,
 in2 => in2,
 out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd" Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type 'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt ‏256 KB
labview project files.zip ‏51 KB

JAEHYLEE (R11i AP) Payables Open Interface Import REJECT CODE:NO TERMS

Purpose
Payables Open Interface Import REJECT CODE:NO TERMS
Symptoms
'EDI' Source로 invoice를 import할때 Payables Open Interface Import program 이 error로 종료된다
정상적인 에러 No Terms로 출력이 되나 , 데이타 상에는 아무 이상이 없으며
debug log file 의 reject code는 NO TERMS INFO라고 출력된다
REJECT CODE:NO TERMS INFO
CauseThe import program in procedure v_check_invalid_terms does not have exception handling. So, when ever it has exceptions like no_data_found or too_many_rows control was returning to the final exception block and the procedure was returning false to the calling procedure. Hence the error instead of Reject reason.
Bug 4704918 - APXIIMPT DOESN'T REJECT INVOICES WITH INCONSISTENT TERMS.
Solution
AP.N이상에서 patch 4755024를 적용
Please apply Patch 4755024 - 1OFF:4704918:AP.N:FP.G:11.5.10:APXIIMPT DOESN'T REJECT INVOICES
Reference
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Please validate BKPF-AWTYP (reference procedure)
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chan

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Message was edited by:
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J2I9 Monthly CENVAT return
J1IG Excise invoice entry at depot
J1IGA Create additional excise entry at depot
J2I5 Extract data for excise registers
J2I6 Print excise registers
rgds
Chidanand

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Code make possible drawing graphs to screen...
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It isn't quite as simple as just "importing" your java code if your goal is to have the forms and the java app communicate with each other. Interaction occurs when a properly designed Java Bean is created.
Take a look at some of the examples on the following page as they can likely provide you with a good starting place:
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Import Export Code

Hai...
Can any one tell where to enter import export code in SAP

Hi,
In Material Master Foreign Trade Import and Foreign Trade export we have to maintain either HS code or IEC number depending on the requirement.
Regards,
Sharan

Important T-codes of SD module

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