Inverting and outputing a finite pulse train

I am using a PCI-6602 card and labview to generate 4 digital finite pulse trains (2MHz to 6MHz range) to be sent to a amplifiing circuit that will drive transducers. I have a VI based on a finite pulse train sample VI I found, but the driver requires both the signal, and the inverted version of the signal. I tired using XOR gates to do this before, but because of rise and fall times, the signals end up overlapping a slight bit, which causes a short between +V and -V supplied to the amplifier. Is there a easy way to have Labview invert my signals while having no overlap? I have access to another PCI-6602 if needed.
I tagged a jpeg of what my VI looks like at the bottom. Any help in this matter would be much appreciated.
Thanks
Attachments:
4xcount.jpg ‏67 KB

You could write out the same signals to the 4 more lines and invert the logic on those lines using a channel property node»digital output»invert lines.
Doug Farrell
Product Manager - Condition Monitoring
National Instruments
National Instruments Condition Monitoring

Similar Messages

How do I output a finite pulse train through multiple counters?

Hello,
I have used LabView examples to create a VI to use with my TIO 6602 that generates a finite pulse train with varying duty cycle, frequency, number of pulse, and initial delay. I can also have it output the pulses through multiple counter channels, but all the channels have the same delay, and are output at the same time. I need each channel to have a specific delay from the first one.
In my VI, I use DAQmx to create a retriggerable finite pulse train by gating a counter with another counter. I have all the neccessary controls over the pulse train, but I can not seem to find an easy way to just copy this waveform and output delayed versions of it to other channels. The delay is very important because these signals will be used to drive ultrasound transducers in a linear array, and for the waveforms to focus at one point, the signal driving the transducers with a shorter distance from the focal point need a larger delay, so that the same waveform arrives from each transducer at the same time.
Any help with how I might do this would be much appreciated.
Thanks!

Hey Sneaky,
Here's a screenshot of the code I put together on how to use multiple counters. Also, take a look here for more information on how to sync multiple counters.
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg ‏67 KB

Finite pulse train, stop and count

Hi, i'm using Labview 8.2 with a DaqCard-6063E on Windows Vista. I generate a finite pulse train with a possibility to stop when ever I want, but how do I do to count the number of pulses?
(The application going to drive a stepper motor forward/backward so I need the number of pulses)
/Pelle

I think you probably mean the 6036e, right? I've got 2 basic ideas for you:
1. Always generate continuous pulses and always count on using your software to decide when to stop. This is *probably* not the solution you want, but it would make life simpler if you can live with it. The reason is that continuous pulse trains only require 1 counter so you can just count those pulses with the 2nd counter. Finite pulsetrains use up both counters. I suspect you need the finite pulsetrain though to define a nominal exact distance, but in case your software decides you must stop prematurely, you'd like to know where you are.
2. Configure an AI task or an AO task that uses your counter output as its sampling clock. Then you can query the AI/AO task for a property like "Total Samples Acquired" or "...Generated" to get your step count. You would do the query with a DAQmx property node -- either a Read or Write property node if I recall correctly (not presently near LV to check). Note also that you should start your AI or AO task before starting the Counter task, and if you stop the counter task, do your query before stopping the AI / AO.
-Kevin P.

Finite pulse train Output

Hi,
I am using a 6602 board and would like to generate a finite pulse train. I have used the example code from Labview (Finite Pulse Train NT-IO) and cannot see both outputs.
I mean I can see the enveloppe on counter +1 (gating counter +0) but cannot see the finite pulse train on Counter +0.
Thanks
W.

Hi
Could you just post you LabVIEW code please
Thanks
Nick

Delayed retriggerable finite pulse train

Hi there,
I'm trying to create a delayed retriggerable finite pulse train on a USB-6251 (2 counters). I just read an old thread on this problem and I got it to work.
However, I'm having this one small annoying issue:
I want to send a finite pulse train (3 pulses) at 1Hz
The trigger has a period of 3seconds (0.333333Hz)
My initial delay is 0.1s
This results in the following :
first 3 seconds : perfect 0.1s delay, 3 pulses at 1Hz
second 3 sec : nothing
third 3 sec : perfect 0.1s delay, 3 pulses at 1Hz
and so on
I reckon this is because the counter that is gating the continuous pulses is not finished yet with his pulse and therefore does not "see" the new rising edge of the trigger.
Is there a way I could solve this?
I know I could just use the first trigger and send 150 pulses or so at 1Hz. That's what I would do if I was very confident in the accuracy of the 3s period of the trigger, but I'm not. And since it is very important the timing is accurate after that trigger, I think I will induce to much error in the timing that way.
Any ideas?
Cheers,
Tom

Sorry for boosting this thread, but I just noticed something in the program Alan suggested : Delayed_Retriggerable_Finite_Pulse_Train.vi while checking its output on a scope:
If you set an initial delay, the pulse train actually starts after 2 times that delay time after the initial trigger. I can't seem to find where this factor 2 is coming from.

What sets no.of pulses in 'finite pulse train' intermediate vi

I want to know how the 'finite pulse train' intermediate vi works. from the VI info I find that counter n generates a continuous clock pulse and is gated by a gating signal coming from counetr n-1. but when I actually run this vi, I find that the counter 2 does not generate a continuous clock pulse and the gating signal is also not used at all for this vi.
I also find that the 'no. of pulses' input does not linearly correspond to the no. of pulses but to the speed of the motor as well. ( I am using the counter to generate a clock train that is used to drive a motor). Nevertheless, when I measure the freq from the output of the counter n , I still find it be to the same as the clock freq that I input thro
ugh my program (and hence independant of step pulses). This is surprising because the speed of the motor changes at constant freq clock trian from counter n.
can anyone tell me whats going on here ?
thanks very much,
Lalitha.

Hello Filipe,
well, here's what I find when I run the vi. I am using a PC-TIO-10 board- so I have given the signals with ref to the pin outputs of this board as well.
I do not get a continuous clock pulse at the output of counter 'n' when I run the program with the gate of counter 'n' tied high all the time.
for instance, I tied gate 2 (pin 5) to high all the time and ran the program. I would have expected a continuous clock pulse to be generated at out 2 (pin 6 ). but only a finite clock pulse whose freq corresponded to the input clock freq was output at OUT 2.
then I tied gate 2 to low and repeated the run- again a finite clock pulse was obtained at OUT 2. It behaved as if the gating signal at gate 2 did not matter at all. All this was while
keeping the gate mode at 'count while high' and the pulse polarity at high (default values).
finally, I also wired out 1 (3) to gate 2 (5) and ran the vi. this is exactly the way the I/O connections should be made as per the vi info. but there was no output at OUT 2 (6) even though the gating signal was observed at OUT 1 and therfore tied to gate 2.
thus my VI is not generating a continous clock pulse at the counter 'n' OUT pin - I always get only a finite clock train and this is regardless of whether the gate of the counter 'n' is tied to high/ low/ OUT of previous counter.
why does this happen ?
thank you
Lalitha.

How to change the frequency of a finite pulse train?

Hi all? I Know I’ve asked once a similar question, but I need a better answer. I would like some ideas or examples on how to modify the example in LV; "Finite Pulse Train Generation - Intermediate for AM9513-Based Devices",so that the frequency can be changed while the VI is executing.
Will i have any problem with I use this VI in a DAQ-STC-Based Devices(E-series)?

Tiano,
I will try to better explain the paragraph on LabVIEW. The original paragraph reads ...
"While in a loop for continuous pulse train generation, make two calls to Counter Set Attribute.vi to set the values for "pulse spec 1" (constant 14) and "pulse spec 2" (constant 15). Following these calls you would make a call to Counter Control.vi with the control code set to "switch cycle" (constant 7). The attached LabVIEW programs demonstrate this flow."
You can make two calls to Counter Set Attribute or you can make a call to Set Pulse Specs which, if you open this VI, you will see that it is just making two calls to Counter Set Attribute. What you are doing with the Counter Set Attribute VIs is setting two registers called "pulse s
pec 1" and "pulse spec 2". These two registers are used to configure the frequency and duty cycle of your output frequency.
The example program which is attached to this Knowledge Base demonstrates how to change the frequency of a continuous generation on the fly. Why continuous? Because changing the frequency of a finite train would be easy. When the train completes it's finite generation you would just change the frequency and run a finite train again. You would not care about the time delay due to reconfiguration of the counter.
If you would like to change the frequency of the pulse train using a knob, this functionality will have to be added in the while loop. The while loop will be continuously checking for the new value of the knob and using the knob value to set the pulse specs.
LabVIEW is a language, and as with learning all new languages (spoken or programatic) there is a lot of learning to be accomplished. The great thing is that LabVIEW is much easier than mo
st languages and the learning curve should be much smaller. Don't fret, you'll be an expert before you know it. Especially since you're tackling a challenging first project.
Regards,
Justin Britten

Learn the number of pulses created in a finite pulse train

Hello
I am using the PCI-6602 Board to produce a finite number of pulses with counter0.
I want to know how many pulses that are already created by the counter, while my program is running and show this number on an indicator on the front panel of my VI.
What is the best way to do this with LabVIEW?
Of course I can use another counter to count the pules and route the output of counter0 to its input.
However I wonder if it is possible to solve the problem without using another counter, because DAQmx internally already uses a second counter to produce the finite pulse train so it should be possible to read this counter, isn't it?
Thanks for every help.

However, I wonder where I can get such detailed Information about the internal functionallity of the DAQ-devices and the DAQmx driver? Please let me know where you get this information from. (So that I can avoid using this forum in the future)
Speaking just for myself --- the source has been generally the school of hard knocks. I started doing a lot of special timer/counter work right around the Y2K timeframe. The legacy driver now known as traditional NI-DAQ was then the only game in town. The programming and terminology under trad. NI-DAQ tends to require you to understand the hardware at a lower level. The programming used more counter-specific terminology like Gate and Source signals.
So for a lot of this stuff, I came into DAQmx with a good understanding of the low-level hardware capabilities, and I just needed to tromp around a bit to find the right syntax. Consequently, I'm not much help for pointing you toward info sources as I haven't relied on them much. Meanwhile, good luck with the self-teaching but don't feel compelled to "avoid using this forum in the future."
-Kevin P.
Message Edited by Kevin Price on 11-01-2007 10:04 AM

Finite Pulse Train TIO-Timing Specs

Howdy everyone,
Got a question regarding the pulse specs of finite pulse generation with a 6602 (TIO chip).
I'm using a slightly modified version of the Finite Pulse Train (NI_TIO).vi found in the examples directory to produce finite pulses.
The slight modifications are to allow for some hardware triggering. I am using counters 2 and 3 to produce a finite pulse train.
My external electronics provides the trigger to the gating counter.
I want all of my timing specs relative to this external pulse.
Let's say I want a delay of 10 seconds until my first output pulse is produced by the output counter; I want pulses to come every 1 sec; Pulses are 0.5 sec wide.
I know from looking into the VI's that the TOTAL delay--ie the time from my external trigger until the time the output counter outputs a 0.5 sec pulse--is equal to the "initial delay (in secs) in the finite pulse specs cluster in the VI plus the interpulse interval minus the pulse width.
Thus, If I enter a value of 10 seconds for initial delay, I actually expect the first pulse to be output at time = 10 +1 - 0.5 sec = 10.5 sec. This is one-half second later than desired, but it is easy to correct.
Now for my real question:
I'm usually looking at pulses coming about 20 msec after the trigger arrives. The pulse interval is 5msec and the pulses are 0.5 msec wide.
Even when I program my counters to get the timing I want with this correction, ie. implement the formula Desired Delay = "Initial Delay" - (pulse interval - pulse width), I still see my pulse arriving late by 1msec. 1 msec is enough that I care to get it right. I don't understand the source of this delay. Does anyone have any idea what could be happening?
It seems totally independent of any parameters I enter for pulse interval, intial delay, pulse width.
Not sure if it matter, but I'm generating this finite pulse train inside of a much larger VI that is busy collecting and displaying data from a 6071E.
Any thoughts/help would be greatly appreciated!

I'm using Traditional DAQ (not DAQmx), so I think points 3 and 4 are not strictly true for my VI.
(I'm am very hesitant at this moment to think about switching over to DAQmx : I"m at the end of my graduate career and don't have the time to overhaul my program at the moment; and my VI works perfectly for my needs..except the 1msec delay. I'll suggest future lab peoples move to mx...)
As I understand, for traditional DAQ:
1. Start the counter -- I believe it will force the output into its idle state (low by default).
2. Trigger edge occurs
3. Output remains in idle state for "initial delay."
4. Output transitions to armed state and remains low for "low time" which is computed/specified by the "frequency" and "duty cycle" specs. So the total delay is the "initial delay" + "low time"
5. Ouput transitions to high state for a time, also determined/computed by the frequency and duty cycle specs.
6.Thereafter, the times will be based on your regular pulse specs, such as low time / high time.
OK, I didn't want to drag the VI into it, but it seems there is no other way; and I really want to know why my timing is not quite as I would expect.
The VI I posted has 3 outter sequence frames. The action, as far as we're concerned in this post, is in outter frame number 3; inner frame number 3, case True, subVI Finite Pulse Train (NI-TIO)-jev4.vi. This VI is "slightly" modified from the example that came packaged with LV "Finite Pulse Train (NI-TIO).vi" The modifcations I made were 1. removed the while loop that checked the status of the counters, because I needed this subVI to return before the pulse train had actually finished executing. 2. Added start trig capability to the gating counter's gate. (Maybe this is the source of the 1msec error?).
There is a variable "stim delay (msec)" that specifies when the first high pulse should be output from the 6602. (device 2 for me.)
To complicate things further, " stim delay" is actually relative to another variable in Neurochip-legacy.vi called "record delay." Record delay specifies the delay between the the arrival of the trigger pulse and start of data acquisition on NI6071E. (had to do this because of the way things are set up in the lab). This trigger pulse is shared with the 6602--it is hardwired in a breakout box to also be routed to my 6602 card. Thus, if the trigger arrives at time = 0, record delay = 20 msec, and stim delay = 40 msec, I would like to see my first output pulse of the train (on the 6602) come at time = 60 msec.
For the time being I have set the "initial delay" = record delay + stim delay - (pulse interval - Ta), where pulse interval is just 1/"frequency" parameter for finite pulse generation, and Ta is the desired width of the output pulse which in turn specifies "duty cycle" parameter. For the moment, I've also hardcoded in a 1msec correction--which was the whole reason for the original post.
Maybe in all this arithmetic and wiring I've made a goof somewhere...if so, maybe a fresh pair of eyes would help.
Ok, so if you are brave enough to check out the code, it is attached.
If you find that you are getting the same result as me, I would love to know it.
If you are getting different result than me, I'd love to know it.
If you see where I went wrong, I'd really love to know where.
Thanks very much
jon
Attachments:
Neurochip-Legacy.vi.zip ‏637 KB

Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
You can use a gated pulse train, which is similar to finite pulse train generation. With finite pulse train generation, you have one pulse for the gate of a counter set to generate a pulse train. The pulse train will only be output based on the gate, so if one pulse appears, you have a finite pulse train. Now, if you make the gate be a pulse train itself, then you can continuously output bursts of pulses. For instance, you can set it up such that the pulses are output when the gate is high. When the gate is low, the counter pulses would pause and when the gate resumes to the high states, your pulses would continue. I've attached a code excerpt for using NI-DAQ function calls to generate a finite pulse train that is in our database. I will see abo
ut getting it put onto the http://www.ni.com/support pages. You can also find more information about the function calls used by referencing the NI-DAQ Help file installed with the NI-DAQ driver software and with the NI-DAQ User Manual, which is available at the web pages.
Regards,
Geneva L.
Applications Engineering
National Instruments
http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

How do I generate two finite pulse trains using counters on PXI-6251

I'm trying to use Counter 0 and Counter 1 on the PXI-6251 to generate two finite pulse trains. But, I get this error: "The specified resource is reserved. The operation could not be completed as specified." See attached example.
Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi ‏32 KB

Hi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
M Series Hardware-Time DIO with Counter Clock Generation
Mark E.
Precision DC Product Support Engineer
National Instruments
Digital Multimeters (DMMs) and LCR Meters
Programmable Power Supplies and Source Measure Units

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

Retriggerable finite pulse train

I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continueous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on between pulse trains, when it should be turned off. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. I use the ActualPeriod of the first re-triggerable pulse to ensure the pulse train ends correctly within window of the first re-triggerable pulse, but it seem to wander. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem. I may have to use a single re-triggerable pulse instead of a re-triggerable pulse train as this work correctly every time. However, multiple pulses creates a finer mist from a fuel injector and is the correct why to modulate a fuel injector. The

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

How do you create a finite pulse train using a FP-CTR-502?

I have recently replaced my FP-PG-522 module with a FP-CTR-502 module, to achieve higher output frequencies (FP-PG-522 max output freq is 5kHz, wheras the FP-CTR-502 max output freq is 16 kHz).
I need to be able to generate a finite pulse train. Has anybody created a finite pulse train using a FP-CTR-502 module before? I have started to look into it, but my ideas so far have been complicated (compared to doing it in a PG module).
Any tips on this would be much appreciated.
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au
Solved!
Go to Solution.

I can answer this question myself!
The answer is in the *OLD* version (July 2000) of the operator's manual for the FP-CTR-502. For some reason, this has been removed from the latest version (June 2003).
See page 11 of this link for more information:
http://www.ni.com/pdf/manuals/322660a.pdf
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au

Finite pulse train (daq-stc).vi makes trouble

Hey, I have some trouble. I try to call the "finite pulse train (daq-stc).vi" from one program. The first time I call it it works fine but when I start the program again and want to call the "finite pulse train (daq-stc).vi" again but this time, for example, with a different frequency I get the following error message:"Error -10122 occured at counter control. POssible reasons: NI-DAQ LV: Invalid paramValue used". The only way to start this vi with a different frequency is to reboot the computer.
I use LabView 5.1.1 and the DAQ interface is PCI 6025e or Daq-Pad 6020e. Any suggestions would be highly appreciated. Thanks!

"Any suggestions would be highly appreciated"
You may want to look into updating NI-DAQ.
The parameter its complaining about (just a guess) may be a hardwired group number. I'm guessing the first call is not shutting down the I/O properly. This means on the second and all subseqqunt calls is attempting to configure an I/O and the goup is already in use, thus your error.
IF all of the guesses are true, then the best solution would be shutown the previous I/O. You may get away with a hack the uses new group numbers, but that will lead to memory leaks eventually.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

Inverting and outputing a finite pulse train

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