Is there "rising edge"-block in labview?

And block down counter? rising edge comes from button, digital line etc..

Hi
I want to detect rising edge of FPGA DIOs(trigger0 in attachment) to the RT side.if rising edge happen i have to send some data to FPGA. For this i took while loop on RT side and read boolean indicator(DIO trigeer 0) from FPGA to RT and inplimented some logic to detect rising edge(plz see in attachment). if this indicator(2v on DIO) is true i am executing true case shown in attachment(dont consider logic inside true case).My problem is on RT side true case(plz see in attached file) is executing for both rising and falling edge.As per the logic imlimented to detect rising true case should execute only for 0v to 2v change on pin but this true case is execute for 2v to 0 v change on DIO pin.Why this happen.Can any one plz tell me.
I am testing this with power supply appalying 0v and 2v across the DIO pin no 86 of sbrio 9606.
Attachments:
FPGA.png ‏163 KB
RT.png ‏151 KB

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Is there a "signal builder" block in labview

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Special Profile.PNG ‏35 KB
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How can I use the pulse train from a 6602 to trigger an niFGEN and niSCOPE on each rising edge of the pulse train?

Hello,
Here is my application: I need to use a 6602 counter/timer to generate a pulse train of certain frequency and duty cycle. On each rising edge of this pulse train, I need to output an arbitrary waveform on Ch. 0 of an niFGEN (5422) AND acquire data from CH. 0 of an niSCOPE (5124). I also need to synchronize the niFGEN and the niSCOPE to the same clock used for the pulse train (6602/ctr0). This process needs to continue until the user stops the system.
I can generate the pulse train using the 6602 just fine using ctr0, but the pulse train shows up on OUT0 by default. When setting up the niFGEN and niSCOPE to trigger on rising/positive slope edge, OUT0 is not an option for either device as a source for the digital rising edge (pulse train). The main options for both are PFI0-3 and RTSI lines.
Questions:
1.) Is there a way that I can direct the pulse train to a location (such as an RTSI line) where BOTH the niFGEN and the niSCOPE can use it as a start trigger for each rising edge? I noticed in MAX that a route can be made between ctr0's internal output and a trigger line and others. If this is a solution, could you please explain how to accomplish this?
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3.) Is setting a reference clock for the niFGEN and the niSCOPE the same thing as synchronizing both devices using the same clock that generated the pulse train? It is not clear to me the difference, and why it would necessarily be useful.
Images of my current front panel and block diagram are attached. If you would rather have the actual VI's just let me know. Any help and/or explanation on this is greatly appreciated. Thanks in advance.
Attachments:
Front_Panel_Control.jpg ‏278 KB
Block_Diagram_Control.jpg ‏263 KB

Hello Cgifford,
Welcome to National Instruments Forums.
To output your signal to the PFI lines,
you can use external connectios between OUT0 and PFI lines. You can also use
the backplane to do so by routing into the same RTSI line.
1)
On the SCOPE and FGEN, the name of the
terminals are actually “PXI Trigger Line x/RTSIx” but on the 6602 you might
need to route the signal using the property:
You can also use the DAQmx route signal which perform the same opperation.
2)
This will depend on the frequency of
your pulse train. If this is lower than about 10 ms, then you can probably
place this on a loop and start and stop the acquisition every time. If the
frequency is higher than this, you will have to use:
- Scripting on the FGEN side (read more)
- MultiRecord Fetch (more information in the scope help file
section “Acquisition Functions Reading versus Fetching”).
3)
The short answer is yes. The longer one
might depend on how tight you need the synchronization to be (us, ns, ps). For
very tight synchronization, you should look into here.
Message Edited by Yardov on 06-18-2007 03:14 PM
Gerardo O.
RF Systems Engineering
National Instruments
Attachments:
property.JPG ‏7 KB

DASYLAB : start acquisition on rising edge during a certain period of time

Hello,
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Morgane Charbonneau.
Solved!
Go to Solution.

Hello,
do you know this link?
http://digital.ni.com/public.nsf/allkb/AE0A4D71F0CD603786256D9C0075B95B?OpenDocument
http://digital.ni.com/public.nsf/allkb/91D44FC21F0DF0CE86256BB1003F6CD9?OpenDocument
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PFI0 Trigger : howto plot PFI0 and record dateTime of Rising Edge ?

Hi,
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I use VS2010, MS2013, DAQmx 14.0 .
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Kind Regards,

Hello Charly,
Yes you could start 2 differents tasks, one analog aquisition to plot your signal and at the same time one numeric like a counter to mesure your rising edges.
Hope this will help you,
Kind regards,
Maxime G. | Application Engineer
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Rising Edge on AO Start

Hi,
I'm using a PXI 6251 Daq card.
On this one, I'm generate on analog output a finite signal.
I would like to initiate a rising edge on PXIx terminal when the Output analog task is realy run.
In fact i would like to provoq an output trigger when the analog task is start.
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Thanks for reply.
Regards
=========================
Bonjour,
Je dispose d'une carte PXI 6251
Sur celle-ci je génére un signal Analogique Finit.
Je souhaite provoquer un front montant sur une sortie PFIX quand la tache de génération à démarrer. Puis que cette sortie tombe à 0 quand la tache est stopée....
Est-ce possible ?
Merci pour vos réponses.
Solved!
Go to Solution.

Hello __KB__,
I think you should start from this example : https://decibel.ni.com/content/docs/DOC-5374
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Regards,
Jérémy C.
National Instruments France
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I need some help configuring the trigger edge for a PXI-2567 using Labwindows/CVI. I have been able to successfully create and execute a scan list using both the ni-switch and daqmx APIs. However, currently the PXI-2567 triggers on the falling edge of an input trigger. I need to configure it to trigger on the rising edge of an input trigger. Every function I could find in the daqmx API for configuring the trigger edge gave a non-fatal runtime error, and I could find no such functions in the ni-switch API.
Any help configuring the input trigger edge on the PXI-2567 using Labwindows/CVI would be appreciated.
Thanks

Hi JonRice,
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I have this signal in input:
I have to do something on rising edge as soon as possible.
My idea is to receive an hw interrupt from the board, and to write an isr soubroutine.
I read about callback function so i write some code.
But when i call:
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                                                "Dev1/Ctr0",
                                                "Dev1/Ctr0",
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                                                1));
I have an error for the ctr0, it seems i can use onli the port0.
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I think that a software thread has a big latency for me, at this point don't need the 6602 board,
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There are 10 kinds of people. Those who understand binary notation, and those who do not.
Solved!
Go to Solution.

Sorry if it's passed a long time, i tryed to do as you suggested, but if i set DAQmx_Val_HWTimedSinglePoint how can i have a continuos acquisition?
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#include <stdio.h>
#include <NIDAQmx.h>
#define DAQmxErrChk(functionCall) if( DAQmxFailed(error=(functionCall)) ) goto Error; else
int32 CVICALLBACK TriggerDetectionCallback(TaskHandle taskHandle, int32 signalID, void *callbackData);
void Cleanup (void);
static TaskHandle taskHandle=0;
int main(void)
    int         error=0;
    int32       read;
    uInt32      data[1000];
    char        errBuff[2048]={'\0'};
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    DAQmxErrChk (DAQmxCreateTask("",&taskHandle));
    DAQmxErrChk (DAQmxCreateCICountEdgesChan(taskHandle,
                                            "Dev1/ctr1",
                                            DAQmx_Val_Rising,
                                            0,
                                            DAQmx_Val_CountUp));
    DAQmxErrChk (DAQmxCfgSampClkTiming(taskHandle,
                                       "/Dev1/PFI35",
                                       1000.0,
                                       DAQmx_Val_Rising,
                                       DAQmx_Val_HWTimedSinglePoint ,
                                       1000));
    DAQmxErrChk (DAQmxRegisterSignalEvent(taskHandle,
                                        DAQmx_Val_SampleClock ,
                                        0,
                                        TriggerDetectionCallback,
                                        NULL)
    // DAQmx Start Code
    DAQmxErrChk (DAQmxStartTask(taskHandle));
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Error:
    puts("");
    if( DAQmxFailed(error) )
        DAQmxGetExtendedErrorInfo(errBuff,2048);
    if( taskHandle!=0 ) {
        // DAQmx Stop Code
        DAQmxStopTask(taskHandle);
        DAQmxClearTask(taskHandle);
    if( DAQmxFailed(error) )
        printf("DAQmx Error: %s\n",errBuff);
    printf("End of program, press Enter key to quit\n");
    getchar();
    return 0;
int32 CVICALLBACK TriggerDetectionCallback(TaskHandle taskHandle, int32 signalID, void *callbackData)
    int32   error=0;
    uInt32 data[200]={0};
    int32   numRead;
    uInt32 i=0;
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        printf("\n%d",data);
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Error:
    if( DAQmxFailed(error) )
        DAQmxGetExtendedErrorInfo(errBuff,2048);
        Cleanup();
        printf("DAQmx Error: %s\n",errBuff);
    return 0;
void Cleanup (void)
    if( taskHandle!=0 )
        // DAQmx Stop Code
        DAQmxStopTask(taskHandle);
        DAQmxClearTask(taskHandle);
        taskHandle = 0;
Message Edited by blacksocket on 30-03-2010 03:56 PM
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Rising edge analysis RS FlipFlop without the Reset

Hello, I am a starter with LabView and am trying to create a rising edge analysis. With the first rising edge of a Boolean Signal (an Input) a variable (and an Output) should be set and the second rising edge should reset this variable. It is like a RS Flip-flop with the second Set Signal as Reset.
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Maybe anyone can help me, Thank You!
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Attachments:
FlipFlop.vi ‏19 KB

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And what was your answer? Please share since somebody else might run into the same issue and this thread might be able to help them.
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How do I perform a trigger that collect the data for every rising edge continuously and then automatically put the data in a .xls file??

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Is there "rising edge"-block in labview?

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